Patents by Inventor Peter Zenon Onufryk

Peter Zenon Onufryk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7827555
    Abstract: A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread. In another configuration, a round robin ranking and a priority ranking are determined for the thread indexes. The thread indexes are then ranked according to the round robin ranking and the priority ranking and the highest ranked thread index of a runnable thread is selected as the scheduled thread.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: November 2, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Mitrajit Chatterjee, Peter Zenon Onufryk, Inna Levit
  • Patent number: 7634774
    Abstract: A system and method for scheduling a thread identifies runnable threads based on precycle signals determined before the scheduling cycle. The thread indexes of the runnable threads are grouped according to the thread priorities of the runnable threads, and the thread indexes are ranked within each group. The runnable threads that will be runnable in the next scheduling cycle are identified based on same cycle signals determined during the scheduling cycle. The highest ranked thread index of the runnable threads that will also be runnable in the next scheduling cycle is selected as the scheduled thread.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: December 15, 2009
    Assignee: Integrated Device Technology, inc.
    Inventors: Peter Zenon Onufryk, Inna Levit
  • Patent number: 7353345
    Abstract: A processor access module receives a data command from an agent located externally of a computing processor and performs a cache operation on a cache memory in the computing processor based on the data command. Alternatively, the processor access module receives a data command from the agent and performs a cache operation on the cache memory based on the data command to store a computer program into the cache memory. The processor access module then receives a boot command from the agent and boots the computing processor to initiate execution of the computer program.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 1, 2008
    Assignee: Integated Device Technology, Inc.
    Inventors: Peter Zenon Onufryk, Cesar Talledo
  • Patent number: 5909369
    Abstract: The states of a distributed finite state machine composed of a plurality of devices are coordinated by a sequence of operations to effect a self-timed cycle. Each device is arranged to apply a voltage over one or more leads and measure the current on the corresponding leads. With the methodology, while engendering self-timed cycles, the number of leads interconnecting the devices is also minimized.
    Type: Grant
    Filed: July 24, 1996
    Date of Patent: June 1, 1999
    Assignee: Network Machines, Inc.
    Inventors: Bhaskarpillai Gopinath, Peter Zenon Onufryk