Abstract: A circuit (1) is described for detecting a reverse current condition of a DCDC converter (2). This circuit uses a simple logic gate such as an AND gate to sense the voltage on a determined node (7) of the DCDC converter, and the propagation of the gated signal (27) is controlled using the timing control signals SW1 and SW2 of the DCDC converter, together with delay cells (16 and 17), to ensure that the positive or negative state of the sensed voltage at said node (7) is propagated cleanly through the logic gate (18), the flip-flop or latch circuit (19) and the up-down counter (29) to the output timing control circuit (25). The up-down counter is incremented or decremented in dependence on the presence or absence of a reverse current condition at said node, and the count value (24) of the up-down counter determines the duration of the on-period of the second-phase timing control signal SW2.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: A circuit (1) is described for detecting a reverse current condition of a DCDC converter (2). This circuit uses a simple logic gate such as an AND gate to sense the voltage on a determined node (7) of the DCDC converter, and the propagation of the gated signal (27) is controlled using the timing control signals SW1 and SW2 of the DCDC converter, together with delay cells (16 and 17), to ensure that the positive or negative state of the sensed voltage at said node (7) is propagated cleanly through the logic gate (18), the flip-flop or latch circuit (19) and the up-down counter (29) to the output timing control circuit (25). The up-down counter is incremented or decremented in dependence on the presence or absence of a reverse current condition at said node, and the count value (24) of the up-down counter determines the duration of the on-period of the second-phase timing control signal SW2.

Abstract: A method adjusts a reference voltage of an electronic circuit based on a band-gap voltage supplied by a first band-gap stage. The band-gap stage includes in a series arrangement, between two terminals of a voltage supply source, a current source connected to a first branch, which includes a first configurable resistor in series with a first diode, and to a second branch, which includes a second configurable resistor connected to a complementary resistor in series with a second diode. The band-gap voltage is supplied to a connection node between the current source and each branch. The current source is a PMOS transistor controlled by an output voltage of a first operational amplifier of a current control loop.

Abstract: The present invention concerns a signal generator circuit powered by a supply voltage and including flip flop means including a first input to which is connected a continuous input signal whose amplitude is defined, a second input to which is connected a clock signal whose duty cycle is defined, and a third, reset input, and outputting an output signal whose duty cycle is that of the clock signal and whose amplitude is that of the input signal, characterized in that said circuit further includes regulating means arranged to compare the output signal to a set point signal representative of the desired duty cycle and to deliver a control signal connected to the third input of the flip flop means so as to activate the reset to modify the duty cycle of the output signal.

Abstract: The method adjusts a reference voltage of an electronic circuit based on a band-gap voltage supplied by a first band-gap stage. The band-gap stage includes a current source connected to a first branch, which includes a first configurable resistor in series with a first diode, and to a second branch, which includes a second configurable resistor connected to a complementary resistor in series with a second diode. The current source is a PMOS transistor controlled by an output voltage of a first operational amplifier of a current control loop. The appropriate binary word for configuring the configurable resistors is determined based on four band-gap voltage values measured at two different temperatures and two resistive values of the resistors configured by the same first binary word and by the same second binary word which is different from the first binary word.