Patents by Inventor Petra Felsner
Petra Felsner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7843035Abstract: An embodiment of a MIM capacitor includes a first insulating layer formed over a wafer and a first capacitor plate formed over the wafer within the first insulating layer. The MIM capacitor further includes a second insulating layer formed over the first insulating layer, a capacitor dielectric formed over the first capacitor plate within the second insulating layer and a second capacitor plate formed over the capacitor dielectric within the second insulating layer. A recess is formed in the second capacitor plate below an upper surface of the second insulating layer and a catalytic activation layer is formed in the recess.Type: GrantFiled: July 30, 2008Date of Patent: November 30, 2010Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Patent number: 7615440Abstract: In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.Type: GrantFiled: September 7, 2007Date of Patent: November 10, 2009Assignee: Infineon Technologies AGInventors: Petra Felsner, Thomas Schafbauer, Uwe Kerst, Hans-Joachim Barth, Erdem Kaltalioglu
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Publication number: 20080290459Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: ApplicationFiled: July 30, 2008Publication date: November 27, 2008Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Patent number: 7436016Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: GrantFiled: August 23, 2005Date of Patent: October 14, 2008Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Publication number: 20070294871Abstract: In a method of fabricating a semiconductor device, a level of metal is formed within an interval dielectric. The level of metal includes a first metal line separated from a second metal line by a region of the interlevel dielectric. The region of interlevel dielectric is removed between the first metal line and the second metal line. A high-k dielectric is formed between the first metal line and the second metal line in the region where the interlevel dielectric was removed such that a capacitor is formed by the first metal line, the second metal line and the high-k dielectric.Type: ApplicationFiled: September 7, 2007Publication date: December 27, 2007Inventors: Petra Felsner, Thomas Schafbauer, Uwe Kerst, Hans-Joachim Barth, Erdem Kaltalioglu
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Patent number: 7268383Abstract: Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.Type: GrantFiled: February 20, 2003Date of Patent: September 11, 2007Assignee: Infineon Technologies AGInventors: Petra Felsner, Thomas Schafbauer, Uwe Kerst, Hans-Joachim Barth, Erdem Kaltalioglu
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Publication number: 20050282346Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: ApplicationFiled: August 23, 2005Publication date: December 22, 2005Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald Friese
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Patent number: 6949442Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: GrantFiled: May 5, 2003Date of Patent: September 27, 2005Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Publication number: 20040224474Abstract: A method for forming a MIM capacitor and a MIM capacitor device formed by same. A preferred embodiment comprises selectively forming a first cap layer over a wafer including a MIM capacitor bottom plate, and depositing an insulating layer over the MIM capacitor bottom plate. The insulating layer is patterned with a MIM capacitor top plate pattern, and a MIM dielectric material is deposited over the patterned insulating layer. A conductive material is deposited over the MIM dielectric material, and the wafer is planarized to remove the conductive material and MIM dielectric material from the top surface of the insulating layer and form a MIM capacitor top plate. A second cap layer is selectively formed over the MIM capacitor top plate.Type: ApplicationFiled: May 5, 2003Publication date: November 11, 2004Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald R. Friese
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Publication number: 20040164339Abstract: Semiconductor devices having capacitors formed of a high-k dielectric and a pair of interconnections on either side of the dielectric are provided along with methods of fabricating such semiconductor devices. The interconnections comprise a via and a metal layer.Type: ApplicationFiled: February 20, 2003Publication date: August 26, 2004Applicant: Infineon Technologies North America Corp.Inventors: Petra Felsner, Thomas Schafbauer, Uwe Kerst, Hans-Joachim Barth, Erdem Kaltalioglu
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Patent number: 6730982Abstract: A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning steps (for Al-via to Cu, Al-pad), including: a) providing a substrate having Cu wires and Cu pads embedded therein; b) selectively depositing a first metallic passivation layer on the top copper surfaces sufficient to prevent Cu oxidation and/or Cu out diffusion; c) depositing a final passivation layer; d) employing lithography and etching of the final passivation layer to cause pad opening of the fuses by exposing the passivated Cu in the bond pad area and in the fuse area; and e) causing additional passivation of open pad and open fuse areas by selective immersion deposition of Au.Type: GrantFiled: March 30, 2001Date of Patent: May 4, 2004Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald Friese
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Publication number: 20020155676Abstract: A MIM capacitor (52) comprising a bottom plate (26), a capacitor dielectric (30) and a top plate (46). The capacitor bottom plate (26) is formed within an insulating layer (20) for a contact via (32) layer. The capacitor top plate (46) is formed within an insulating layer (34) of a metallization layer. The MIM capacitor (52) may be fabricated without the use of additional processes and patterning masks.Type: ApplicationFiled: April 19, 2001Publication date: October 24, 2002Inventors: Michael Stetter, Petra Felsner, Andreas Augustin, Gabriela Brase, Andy Cowley, Gerald Friese
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Publication number: 20020142592Abstract: A process of making an interconnection structure of Cu FBEOL semiconductor devices that does not rely upon Al-wirebond pads which require additional patterning steps (for Al-via to Cu, Al-pad), comprising:Type: ApplicationFiled: March 30, 2001Publication date: October 3, 2002Inventors: Hans-Joachim Barth, Petra Felsner, Erdem Kaltalioglu, Gerald Friese
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Patent number: 6451664Abstract: A method of making a metal-insulator-metal (MIM) capacitor (158) having self-passivating plates (143, 155). A liner (116) is deposited on a workpiece (112) and dielectric (114). A conductive layer (142) is deposited and annealed to form dopant-rich region (144). Insulating region (145) is formed on exposed portions of dopant-rich region (144) by exposure to atmosphere or oxygen. Capacitor dielectric layer (146) is disposed over the first capacitive plate (143). A second capacitive plate (155) is formed over the first capacitive plate (143) and capacitor dielectric layer (146). The second capacitive plate (155) is annealed to form dopant-rich region (154) and exposed to atmosphere or oxygen to form insulating region (156). Optional seed layer (140) may be deposited prior to the formation of the first capacitive plate (143).Type: GrantFiled: January 30, 2001Date of Patent: September 17, 2002Assignee: Infineon Technologies AGInventors: Hans-Joachim Barth, Gerald Friese, Petra Felsner
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Publication number: 20020102809Abstract: A metal-insulator-metal (MIM) capacitor (158) having self-passivating plates (143, 155). A liner (116) is deposited on a workpiece (112) and dielectric (114). A conductive layer (142) is deposited and annealed to form dopant-rich region (144). Insulating region (145) is formed on exposed portions of dopant-rich region (144) by exposure to atmosphere or oxygen. Capacitor dielectric layer (146) is disposed over the first capacitive plate (143). A second capacitive plate (155) is formed over the first capacitive plate (143) and capacitor dielectric layer (146). The second capacitive plate (155) is annealed to form dopant-rich region (154) and exposed to atmosphere or oxygen to form insulating region (156). Optional seed layer (140) may be deposited prior to the formation of the first capacitive plate (143).Type: ApplicationFiled: January 30, 2001Publication date: August 1, 2002Inventors: Hans-Joachim Barth, Gerald Friese, Petra Felsner