Abstract: Stabilized pharmaceutical formulations of insulin analogues and/or insulin derivatives are disclosed.

Abstract: The application relates to an aqueous pharmaceutical formulation comprising 200-1000 U/mL [equimolar to 200-1000 IU human insulin] of insulin glargine.

Abstract: The application relates to an aqueous pharmaceutical formulation comprising 200-1000 U/mL [equimolar to 200-1000 IU human insulin] of insulin glargine.

Abstract: The application relates to an aqueous pharmaceutical formulation comprising 200-1000 U/mL [equimolar to 200-1000 IU human insulin] of insulin glargine.

Abstract: The present invention relates to a method for forming high quality oxide layers of different thickness over a first and a second semiconductor region in one processing step. The method comprises the steps of: doping the first and the second semiconductor region with a different dopant concentration, and oxidising, during the same processing step, both the first and the second semiconductor region under a temperature between 500° C. and 700° C., preferably between 500° C. and 650° C. A corresponding device is also provided. Using a low-temperature oxidation in combination with high doping levels results in an unexpected oxidation rate increase.

Abstract: A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Abstract: There is a method of manufacturing a semiconductor device with a semiconductor body comprising a semiconductor substrate and a semiconductor region which are separated from each other with an electrically insulating layer which includes a first and a second sub-layer which, viewed in projection, are adjacent to one another, wherein the first sub-layer has a smaller thickness than the second sub-layer, and wherein, in a first sub-region of the semiconductor region lying above the first sub-layer, at least one digital semiconductor element is formed and, in a second sub-region of the semiconductor region lying above the second sub-layer, at least one analog semiconductor element is formed. According to an example embodiment, the second sub-layer is formed in that the lower border thereof is recessed in the semiconductor body in relation to the lower border of the first sub-layer Fully depleted SOI devices are thus formed.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising a semiconductor substrate (2) and a semiconductor region (3) which are separated from each other by means of an electrically insulating layer (4) which comprises a first and second sublayer (4A, 4B) that are viewed in projection adjacent to each other, whereby the first sublayer (4A) is provided with a smaller thickness than the second sublayer (4B) and whereby in a first subregion (3B) of the semiconductor region (3) lying above the first sublayer (4A) at least one digital semiconductor element (5) is formed and in a second subregion (3B) of the semiconductor region (3) lying above the second sublayer (4B) at least one analogue semiconductor element (6) is formed. According to the invention the second sublayer (4B) is formed in such a way that the lower border thereof is in relation to the lower border of the first sublayer (4A) formed sunken in the semiconductor body (1).

Abstract: A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.

Abstract: A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Abstract: A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.