Abstract: Systems and methods for operating an RPA (robotic process automation) services delivery platform for implementing a plurality of RPA services on premises of a customer are provided. An installer for installing a plurality of RPA services on one or more computing systems located on premises of a customer is generating using the RPA services delivery platform. One or more of the plurality of RPA services installed on the one or more computing systems using the installer are maintained using the RPA services delivery platform.

Abstract: An integrated circuit (IC) package includes electrical contacts disposed at a first surface of the IC package, an integrated circuit implementing an electrical signaling interface, and a connector assembly accessible at a second surface of the IC package. The connector assembly is to mechanically attach to another connector assembly and includes contact terminals electrically coupled to the electrical signaling interface. The connector assembly can be configured to provide friction coupling with the other connector assembly to permit the other connector assembly to be removably attached. A system includes the IC package and an external transceiver module having a connector assembly mechanically attached to the connector assembly of the IC package. The electrical signaling interface conducts signaling with the external transceiver module in accordance with one signal format and the external transceiver module conducts signaling over a transmission medium in accordance with another signal format.

Abstract: Methods and apparatus provide for testing an integrated circuit including an input/output (I/O) interface. The method and apparatus place the I/O interface in a test mode by test enabling logic. During the test mode, the method and apparatus also provide, by a clock generator in the I/O interface, an internal phase-aligned receiver clock signal to a plurality of transceivers in the I/O interface. The clock generator is a transmitter portion of one of the plurality of transceivers in the I/O interface. The method and apparatus then monitor for errors in loopback data from the plurality of transceivers in the I/O interface by an automatic test equipment (ATE). The phase of the internal phase-aligned receiver clock signal is aligned with the loopback data of the plurality of transceivers, and the frequency of the internal phase-aligned receiver clock signal may be above about 200 MHz.

Abstract: The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Abstract: A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.

Abstract: The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the high speed of operation, all circuits including the phase locked loop, operate as differential circuits, which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.

Abstract: The invention provides a method for utilizing the Inter Packet Gaps (IPGs) to create an Extended Link Monitoring Channel in a physical layer transceiver for a 10 Gb/s Ethernet link for communicating link related information, thus providing an extensive link maintenance capability. A corresponding transceiver between an Ethernet media access control (MAC) layer device and a 10 Gb/s Ethernet link, comprising a physical coding sublayer (PCS) extension circuit for implementing the Extended Link Monitoring Channel is also provided.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the high speed of operation, all circuits including the phase locked loop, operate as differential circuits, which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.

Abstract: Quake Transistor Logic (QTL) circuits of the embodiments of the invention are low power, high-speed circuits that can be manufactured by the same process as the lower-speed complex circuits, and are thus capable of being integrated on the same device. A number of techniques are employed to give QTL circuits their unique advantages. Lower power without loss of speed is achieved through the use of a self-biasing clock buffer to eliminate the need for tail current sources in the logic; differential signals are employed throughout to improve noise immunity with a low logic signal swing; an optional tuning circuit provides extension of the frequency response to achieve an even higher clock frequency and logic circuit bandwidth.

Abstract: The invention relates to a driver circuitry suitable for controlling an operation of a laser or an optical modulator and providing extended dynamic range of the output power and enhanced quality of the output signal. It comprises a power control unit, a pre-driver stage and an output stage. The pre-driver stage and the output stage include differential amplifiers, the output stage amplifier preferably having a cascode configuration. The pre-driver stage provides a preliminary amplification of an input signal which is received and further amplified by the output stage. The power control unit operates in response to a reference signal, e.g. variable DC voltage or a feedback signal, and generates two control signals which control operating points of the pre-driver and the output stage in such a manner that higher output power of the driver corresponds to the higher output signal from the pre-driver stage. Conveniently, both the pre-driver stage and the output stage may be controlled by the same control signal.

Abstract: The invention relates to a driver circuitry suitable for controlling an operation of a laser or an optical modulator and providing extended dynamic range of the output power and enhanced quality of the output signal. It comprises a power control unit, a pre-driver stage and an output stage. The pre-driver stage and the output stage include differential amplifiers, the output stage amplifier preferably having a cascode configuration. The pre-driver stage provides a preliminary amplification of an input signal which is received and further amplified by the output stage. The power control unit operates in response to a reference signal, e.g. variable DC voltage or a feedback signal, and generates two control signals which control operating points of the pre-driver and the output stage in such a manner that higher output power of the driver corresponds to the higher output signal from the pre-driver stage. Conveniently, both the pre-driver stage and the output stage may be controlled by the same control signal.

Abstract: A gain control amplifier includes an input differential circuit having a pair of transistors, the emitters of which are coupled via a pair of emitter resistors. The input differential circuit includes a current sink for providing an operating current. With variation of the operating current, the gain control amplifier's gain is varied. Two emitter coupled differential amplifiers are connected to the input differential circuit having a current sink. A current flowing in the transistors of the emitter coupled differential amplifier and the input differential circuit is split by an additional emitter coupled differential circuit having a current sink. A current splitting factor is controlled in response to the voltage difference between the collectors of the two transistors of the two emitter coupled differential amplifiers. Since the relatively small currents flow in the emitter resistors, noise caused thereby is relatively low. Thus, it provides a wide input dynamic range with low noise.

Abstract: An RC circuit with voltage controlled delay is provided. The circuit comprises a matched pair of RC delay elements, driven by outputs of a pair of amplifiers comprising a fixed gain amplifier and a variable gain amplifier having gain m so that the delay is dependent on a gain control voltage. Preferably, the circuit is operable in a regime wherein the gain m is linearly dependent on an input control voltage so that the circuit delay is also linearly dependent on the input control voltage. Advantageously, where the amplifier gain has non-linear dependence on a gain control voltage, a control voltage generator comprising a linear to logarithmic converter is used to provide an effective linear operation in response to an input control voltage. The circuit is preferably operated in differential mode, with RC circuit elements implemented simply as resistors and capacitors, and the amplifier and active elements provided by bipolar transistors.

Abstract: In methods and apparatus for controlling a phase relationship of two signals, a supplementary phase adjustment signal is generated. The supplementary phase adjustment signal has a zero value when an actual phase relationship of the two signals deviates from a desired phase relationship by less than a threshold phase deviation, and has a non-zero value when the actual phase relationship deviates from the desired phase relationship by more than the threshold phase deviation. The phase relationship of the two signals is adjusted in response to a sum of the supplementary phase adjustment signal and a phase adjustment signal which is proportional to the deviation of the actual phase relationship from the desired phase relationship. The methods and apparatus are particularly applicable to alignment of clock signals with data signals.