Patents by Inventor Petros Daniel Fernandes de Medeiros Félix

Petros Daniel Fernandes de Medeiros Félix has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Formal verification with EDA application and hardware prototyping platform
    Patent number: 11138357
    Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: October 5, 2021
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Tulio Paschoalin Leao, Petros Daniel Fernandes de Medeiros Félix, Julia Pinheiro de Oliveira, Arthur Ribeiro Araujo, Lucas Martins Chaves, Andrei dos Santos Silva, Pablo Nunes Agra Belmonte