Abstract: A controller chip includes a first cluster including one or more first controller units, a first power supply grid, a first clock tree structure to supply one or more clock signals, and at least a first power supply input. A second cluster includes one or more second controller units, a second power supply grid, a second clock tree structure to supply one or more clock signals, and at least a second power supply input. A monitoring cluster includes a monitoring circuit configured to: monitor the power supply and the clock signal supply of each of the first cluster and second cluster, and in the event of determining at least one of a power supply failure or a clock signal supply failure in one cluster of the first cluster or the second cluster, indicate the failure to the other cluster to take one or more actions.