Patents by Inventor Petrus H. C. Magnee
Petrus H. C. Magnee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8580596Abstract: The present invention relates to a method of forming a micro cavity having a micro electrical mechanical system (MEMS) in a process, such as a CMOS process. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters. The oscillators can be used in time-keeping and frequency reference applications such as RF modules in mobile phones, devices containing blue-tooth modules and other digital and telecommunication devices.Type: GrantFiled: April 10, 2009Date of Patent: November 12, 2013Assignee: NXP, B.V.Inventors: Petrus H. C. Magnee, Jan Jacob Koning, Jozef T. M. Van Beek
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Patent number: 8084829Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5).Type: GrantFiled: April 20, 2005Date of Patent: December 27, 2011Assignee: NXP B.V.Inventors: Wibo D. Van Noort, Petrus H. C. Magnee, Lis K. Nanver, Celine J. Detcheverry, Ramon J. Havens
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Publication number: 20100258882Abstract: The present invention relates to a method of forming a micro cavity having a micro electrical mechanical system (MEMS) in a process, such as a CMOS process. MEMS resonators are being intensively studied in many research groups and some first products have recently been released. This type of device offers a high Q-factor, small size, high level of integration and potentially low cost. These devices are expected to replace bulky quartz crystals in high-precision oscillators and may also be used as RF filters.Type: ApplicationFiled: April 10, 2009Publication date: October 14, 2010Applicant: NXP, B.V.Inventors: PETRUS H. C. MAGNEE, JAN JACOB KONING, JOZEF T. M. VAN BEEK
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Publication number: 20080173974Abstract: The invention relates to a semiconductor device (10) comprising a semiconductor body (1) with a high-ohmic semi-conductor substrate (2) which is covered with a dielectric layer (3, 4) containing charges, on which dielectric layer one or more passive electronic components (20) comprising conductor tracks (20) are provided, wherein, at the location of the passive elements (20), a region (5) is present at the interface between the semiconductor substrate (2) and the dielectric layer (3, 4), as a result of which the conductivity of an electrically conducting channel induced in the device (10) by the charges is limited at the location of the region (5). According to the invention, the region (5) is formed by deposition and comprises a semi-insulating material. As a result, the device (10) has a very low high-frequency power loss because the inversion channel is formed in the semi-insulating region (5).Type: ApplicationFiled: April 20, 2005Publication date: July 24, 2008Applicant: KONINKLIJKE PHILIPS ELETRONICS N.V.Inventors: Wibo D. Van Noort, Petrus H.C. Magnee, Lis K. Nanver, Celine J. Detcheverry, Ramon J. Havens
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Patent number: 6777780Abstract: The invention relates to a trench bipolar transistor structure, having a base 7, emitter 9 and collector 4, the latter being divided into a higher doped region 3 and a lower doped drift region 5. An insulated gate 11 is provided to deplete the drift region 5 when the transistor is switched off. The gate 11 and/or doping levels in the drift region 5 are arranged to provide a substantially uniform electric field in the drift region in this state, to minimise breakdown. In particular, the gate 11 may be seminsulating and a voltage applied along the gate between connections 21,23.Type: GrantFiled: July 25, 2002Date of Patent: August 17, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Raymond J. E. Hueting, Jan W. Slotboom, Petrus H. C. Magnee
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Patent number: 6774434Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.Type: GrantFiled: November 12, 2002Date of Patent: August 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Raymond J. E. Hueting, Jan W. Slotboom, Petrus H. C. Magnee
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Publication number: 20030094649Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.Type: ApplicationFiled: November 12, 2002Publication date: May 22, 2003Applicant: KONINKLIJKE PHILIPS ELECTRONICSInventors: Raymond J.E. Hueting, Jan W. Slotboom, Petrus H.C. Magnee
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Patent number: 6551890Abstract: A method of manufacturing a semiconductor device comprising a poly-emitter transistor (1) and a capacitor (2). A base electrode (14), a first electrode (16, 37) and an emitter window (18) are formed at the same time in a first polysilicon layer (13) covered with an insulating layer (25). Subsequently, the side walls of the electrodes (20, 39) and the wall (23) of the emitter window are covered at the same time with insulating spacers (22, 44) by depositing a layer of an insulating material, followed by an anisotropic etching process. The base (8) of the transistor is formed by ion implantation. The emitter (9) is formed by diffusion, from an emitter electrode (30) formed in a second polysilicon layer. Preferably, the first electrode of the capacitor consists of mutually connected strips (37).Type: GrantFiled: March 7, 2000Date of Patent: April 22, 2003Assignee: Koninklijke Philips Electronics N.V.Inventors: Ronald Dekker, Petrus H. C. Magnee
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Publication number: 20030030488Abstract: The invention relates to a trench bipolar transistor structure, having a base 7, emitter 9 and collector 4, the latter being divided into a higher doped region 3 and a lower doped drift region 5. An insulated gate 11 is provided to deplete the drift region 5 when the transistor is switched off. The gate 11 and/or doping levels in the drift region 5 are arranged to provide a substantially uniform electric field in the drift region in this state, to minimise breakdown. In particular, the gate 11 may be seminsulating and a voltage applied along the gate between connections 21,23.Type: ApplicationFiled: July 25, 2002Publication date: February 13, 2003Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Raymond J.E. Hueting, Jan W. Slotboom, Petrus H.C. Magnee