Abstract: A temperature compensated oscillator circuit includes an oscillator (1) which is controlled by a processor (8) . The output frequency (fx) of the oscillator (1) or an external reference frequency (fref) are used as reference signal in conjunction with a dual mode oscillator (9) which can be switched to provide temperature dependent fundamental (f1) and third (f3) harmonic frequencies. By the use of switches (S1, S2 S3), a divider (2) and first and second counters (3, 10) both calibration and temperature compensation of the oscillator (1) are carried out via the processor (8), using the substantially linear temperature dependence of the frequency difference between the third harmonic (f3) and three times the fundamental frequency (3f1).

Abstract: A switched capacitor network includes an input terminal (2) an output terminal (2), a series arrangement of a first and a second switching transistor, each having a control electrode (S.sub.1) for receiving a first (S.sub.1 ) and a second switching signal, respectively, and a capacitance between the junction point of the two switching transistors and a point of constant potential. The two switching transistors have a zone in common and the capacitance (S.sub.s) is exclusively constituted by the parasitic capacitance of the zone (17). This structure results in a switched capacitor network with an increased time constant.

Abstract: Dematrixing circuit of the switched-capacitor type for dual channel TV stereo sound signals comprising first and second signal inputs (I.sub.1, I.sub.2) for applying a stereo sum signal ##EQU1## thereto and one of the two left and right stereo signals (for example, R), the amplitude of said latter stereo signal being twice as high as that of each of the two stereo signals in the stereo sum signal, and comprising first and second signal outputs (O.sub.1, O.sub.2) for supplying a dematrixed stereo signal. In order to provide the possibility of a correct dematrixing of the stereo signal (L), which is not separately available, with a minimum number of circuit elements and to simultaneously avoid through-connections from the two signal inputs (I.sub.1, I.sub.2) at one end and the two signal outputs (O.sub.1, O.sub.2) at the other end, the dematrixing circuit according to the invention comprises first and second capacitors (C.sub.1, C.sub.2) each being arranged between an input switch (S.sub.i1, S.sub.