Abstract: A semiconductor structure for a photonic integrated circuit, comprising: a substrate; a waveguide on the substrate; a passive region comprising a first cladding layer in contact with a first portion of the waveguide; and an active region comprising a second cladding layer different to the first cladding layer, the second cladding layer in contact with a second portion of the waveguide and the first cladding layer. There is a photonic integrated circuit comprising the semiconductor structure. There is a method of manufacturing a semiconductor structure for a photonic integrated circuit.

Abstract: A structure for a photonic integrated circuit, comprising: a substrate; a first portion of n-type semiconductor material on a first surface area of the substrate, a second portion of n-type semiconductor material on a second surface area of the substrate; a waveguide; and an element between the first portion and the second portion. The waveguide is on and in contact with the element. The element is configured to reduce electric current flow from the first portion to the second portion during propagation of light via the waveguide.

Abstract: A method of fabricating a semiconductor structure with multiple quantum wells, comprising: providing a substrate comprising a binary semiconductor compound having a first lattice constant; depositing: a first layer on the substrate, the first layer of a first semiconductor alloy, and a second layer in contact with the first layer, the second layer of a second semiconductor alloy, to form a first stack of substantially planar semiconductor layers on the substrate; depositing in contact with the first stack a third layer of a binary semiconductor compound having the first lattice constant; depositing at least: a fourth layer on the third layer, the fourth layer comprising a third semiconductor alloy comprising InP, and a fifth layer in contact with the fourth layer, the fifth layer comprising a fourth semiconductor alloy comprising InP, to form a second stack of substantially planar semiconductor layers on the third layer.