Abstract: A device may include an intercept-temperature drift input to receive an intercept-temperature drift value. The device may further include a reference current generator that generates a reference current based at least in part on the intercept-temperature drift value. Additionally, the device may include an analog signal chain that adjusts a slope-temperature drift of the signal-strength detector by adjusting a delta proportional to absolute temperature of the analog signal chain.

Abstract: A device may include an analog signal chain that adjusts a slope-temperature drift of the signal-strength detector by adjusting a delta proportional to absolute temperature of the analog signal chain. The device may further include an intercept-temperature drift input to receive an intercept-temperature drift value. Additionally, the device may include a reference current generator that generates a reference current based at least in part on the intercept-temperature drift value.

Abstract: Logarithmic current-to-voltage converters with emitter resistance compensation are disclosed herein. In certain embodiments, a logarithmic current-to-voltage converter includes a logarithmic bipolar transistor that converts an input current to a logarithmic voltage, and an emitter resistance compensation circuit that includes a replica of the logarithmic bipolar transistor. The emitter resistance compensation circuit processes a copy of the input current to generate an emitter resistance compensation signal that adjusts the logarithmic voltage to correct for an error introduced by an emitter resistance of the logarithmic bipolar transistor. By providing emitter resistance compensation in this matter, logarithmic current-to-voltage conversion with high accuracy and low log error is achieved.

Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.

Abstract: In a variable gain amplifier, a base of a bipolar first transistor receives a first differential input signal. The emitter of the first transistor is connected in series between a first resistor and a MOSFET coupled to ground. An output of the amplifier is a current through the collector. The conductivity of the MOSFET controls a gain of the amplifier. A bipolar second transistor receives a second differential input signal, and the second transistor provides a modulated gate voltage to the MOSFET. The drain voltage of the MOSFET is modulated by the first differential input signal and thus undesirably generates distortion. To reduce the distortion, the modulated gate voltage causes the AC component for a certain DC voltage at the drain of the MOSFET to be lowered, improving linearity. Since no current source is used, the amplifier has a large headroom, allowing operation using a low operating voltage.

Abstract: In a variable gain amplifier, a base of a bipolar first transistor receives a first differential input signal. The emitter of the first transistor is connected in series between a first resistor and a MOSFET coupled to ground. An output of the amplifier is a current through the collector. The conductivity of the MOSFET controls a gain of the amplifier. A bipolar second transistor receives a second differential input signal, and the second transistor provides a modulated gate voltage to the MOSFET. The drain voltage of the MOSFET is modulated by the first differential input signal and thus undesirably generates distortion. To reduce the distortion, the modulated gate voltage causes the AC component for a certain DC voltage at the drain of the MOSFET to be lowered, improving linearity. Since no current source is used, the amplifier has a large headroom, allowing operation using a low operating voltage.

Abstract: A poly-phase filter receives inphase input signals I and ? and quadrature input signals Q and Q, and provides inphase output signals Iout and Iout and quadrature output signals Qout and Qout. The capacitance of each variable capacitor connected to the terminals providing inphase output signals Iout and Iout is and the capacitance of each variable capacitor connected to the terminals providing quadrature output signals Qout and Qout, are different in value, and preferably by twice a predetermined value. This is because adjustment to the capacitance values may be made to each set of variable capacitors by the predetermined value.

Abstract: A single-balanced balun mixer circuit includes a balun with a center tap connected to a differential pair with a tail resistor. The balun receives a first input signal and a second signal at the single-ended input terminal and the center tap, respectively. Such a balun mixer may be used as an up-converter mixer by supplying a baseband or intermediate signal at the center tap and a local oscillator (LO) signal at the single-ended input terminal.

Abstract: A single-balanced balun mixer circuit includes a balun with a center tap connected to a differential pair with a tail resistor. The balun receives a first input signal and a second signal at the single-ended input terminal and the center tap, respectively. Such a balun mixer may be used as an up-converter mixer by supplying a baseband or intermediate signal at the center tap and a local oscillator (LO) signal at the single-ended input terminal.

Abstract: A poly-phase filter receives inphase input signals I and ? and quadrature input signals Q and Q, and provides inphase output signals Ilow and Iout and quadrature output signals Qout and Qout. The capacitance of each variable capacitor connected to the terminals providing inphase output signals Iout and Iout is and the capacitance of each variable capacitor connected to the terminals providing quadrature output signals Qout and Qout, are different in value, and preferably by twice a predetermined value. This is because adjustment to the capacitance values may be made to each set of variable capacitors by the predetermined value.

Abstract: A mixer in an RF demodulator includes a transconductance amplifier that converts an RF input voltage (Vin), applied to the base of a first bipolar transistor, to a first output current. The first output current contains third order intermodulation (IM3) products. An IM3 canceller is connected in parallel with the transconductance amplifier. The base of a second bipolar transistor in the IM3 canceller is coupled to the DC component of Vin, and the AC component of Vin is coupled to the emitter of the second bipolar transistor, such that the currents though the first bipolar transistor and the currents through the second bipolar transistor change oppositely. The collectors of the transistors are coupled together. The values of components in the IM3 canceller are set so that the current generated by the IM3 canceller substantially cancels IM3 distortion in the first current or other current generated in a demodulator of Vin.

Abstract: A power mixer architecture for a transmitter chip is disclosed. The power mixer architecture is a mixing stage including one or more upper trees, and one or more lower trees. Each lower tree is selectively activated to receive current biasing signals, and current intermediate frequency signals. Upon receipt, the activated lower tree activates a corresponding upper tree to receive one or more amplified current intermediate frequency signals from the lower tree. In conjunction with a reception of voltage local oscillating signals, the upper tree provides voltage radio frequency signals. The gain of the lower tree is designed to be constant over any variance in a temperature, supply voltage or processing performance of the transmitter chip.

Abstract: A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

Abstract: A received signal strength indicator operating at low intermediate of zero intermediate frequency is provided. The received signal strength indicator forms absolute values from an in-phase signal component and a quadrature signal component of a low or zero intermediate frequency signal that represents a received radio frequency signal. The absolute values are added. Logarithmic signal processing is performed either before absolute signal forming or after adding. Finally, low pass filtering is performed.

Abstract: A power mixer architecture for a transmitter chip is disclosed. The power mixer architecture is a mixing stage including one or more upper trees, and one or more lower trees. Each lower tree is selectively activated to receive current biasing signals, and current intermediate frequency signals. Upon receipt, the activated lower tree activates a corresponding upper tree to receive one or more amplified current intermediate frequency signals from the lower tree. In conjunction with a reception of voltage local oscillating signals, the upper tree provides voltage radio frequency signals. The gain of the lower tree is designed to be constant over any variance in a temperature, supply voltage or processing performance of the transmitter chip.

Abstract: A quadrature modulator with set-and-forget carrier leakage compensation. The quadrature modulator comprises an in-phase and a quadrature branch. In the in-phase and quadrature branches, real-time digital signals are converted to analog signals, the analog signals are filtered, and the filtered analog signals are modulated with a carrier signal and a ninety degrees phase shifted version of the carrier, respectively. The modulated in-phase and quadrature signals are added so as to form a quadrature amplitude modulated signal. Preferably upon powering up of the quadrature modulator, in the in-phase and quadrature branches, carrier leakage is measured. The measured carrier leakage is supplied to comparators, which toggle, when carrier leakage is minimal in the respective in-phase and quadrature branches.