Patents by Inventor Pey Fang Hiew

Pey Fang Hiew has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014123
    Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Kuan-Hsiang Mao, Chin Teck Siong, Pey Fang Hiew, Wen Yuan Chuang, Sharon Huey Lin Tay, Wen Hung Huang
  • Publication number: 20150206829
    Abstract: A packaged semiconductor device has a lead frame, a semiconductor die, and bond wires. The lead frame has a two-dimensional array of leads with a subset of interior leads located in the interior of the array that do not extend to the perimeter of the array. The bond wires are connected to the semiconductor die and respective ones of the leads of the array.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Inventors: Yin Kheng Au, Seoh Hian Teh, Jia Lin Yap, Pey Fang Hiew, Ly Hoon Khoo
  • Patent number: 8853840
    Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap
  • Publication number: 20140231978
    Abstract: A semiconductor die has outer leads with an outer lead external connection section and an outer lead bonding section. Inner leads are spaced from the outer leads. Each of the inner leads has an inner lead external connection section spaced and downset from an inner lead bonding section. A non-electrically conductive die mount is molded onto upper surface areas of each inner lead external connection section. A semiconductor die is mounted on the non-electrically conductive die mount and bond wire provide interconnects for selectively electrically connecting bonding pads of the die to the inner lead bonding sections and at least one outer lead bonding section. A mold compound covers the semiconductor die, the bond wires, and the outer and inner lead bonding sections.
    Type: Application
    Filed: February 21, 2013
    Publication date: August 21, 2014
    Inventors: Yin Kheng Au, Pey Fang Hiew, Jia Lin Yap