Abstract: Disclosed is a method for making a mushroom gate for a microwave transistor. Three masking layers are deposited on the semiconductor body of a transistor. At least two of these masking layers are different and have selective solvents. After the opening of the external layer, the intermediate layer is dissolved with sub-etching with respect to the external layer, then the base of the gate is etched in the internal layer. The edges of the sub-etching prevent the metal deposited on the mask from adhering to the gate, thus facilitating the lift-off of the mask. Application to microwave transistors with symmetrical or disymmetrical mushroom gate.

Abstract: In a cascaded analog-digital converter, a first ADC determines the most significant bits. To determine the least significant bits, in a second ADC, it is necessary to assess the difference between the input analog signal V.sub.E and its already digitized part, reconverted into analog form. The subtractor/amplifier receives, firstly, the input signal V.sub.E which is converted into a current i.sub.E and, secondly, the most significant bits on a digital-analog converter. This constitutes a source, capable of being modulated, which gives a current i.sub.c. Two parallel-mounted transistors differentiate between the current i.sub.c of the source capable of being modulated and the current i.sub.E corresponding to the input signal V.sub.E, and amplify it. The disclosure is applicable to cascaded ADCs.

Abstract: Disclosed is a device enabling a transistor of submicronic gate length to be constructed using optical means of masking. The process includes a stage during which a resin, deposited on a wafer of semiconducting materials, is etched in order to isolate a pattern as a future gate mask. The mask is eroded, and a layer of silica deposited. Because of the erosion, the sides of the pattern and of the mask are inclined. After etching of the layer of silica and the masking resin, there remain therefore two silica masks whose sloping sides leave a submicronic aperture, through which the gate is deposited.

Abstract: A digital/analog converter designed for very high frequencies is described. It has a first stage, which is a standard stage, in which several parallel-mounted controllable loads deliver currents in geometrical progression in a current/voltage converting transistor. Each controllable load has an input transistor, to the gate of which a bit is addressed as well as a diode and a saturable resistor. The second stage is a shifter formed by a transistor mounted as a follower source, in series with at least one diode and one pull-back transistor, the source of which is at a negative potential. The voltage at the drain of the converting transistor is applied to the gate of the shifter transistor, and the output voltage at the drain of the pull-back transistor is looped to the gate of the converting transistor.

Abstract: In an analog-digital converter working at microwave frequencies, the input signal is addressed in parallel to bit levels which are in cascade with one another. Each bit level has a transducer which converts the voltage into a current, and compares this current with a calibrated source. The resultant current is addressed to a logic circuit, the output of which delivers a bit. An intermediate output of the logic circuit constitutes a control signal which regulates the currents of the analog comparators of the less significant bit levels. The calibrated currents are in geometrical progression.

Abstract: A microwave linear amplifier is described. Its pass band is equal to that of the transistors which constitute it, without being limited by the usual biasing circuits which comprise chokes and capacitors with a narrow pass band. In this amplifier, which has at least one input transistor, the gate bias at neutral point is provided by a BFL type circuit, generally used in logic circuits, the output of which is looped to the input. The input signal is applied both to the inverter transistor of the BFL circuit and to the input transistor. The same BFL circuit used in the amplification stage provides for the self-matching of the stages which can be cascaded.

Abstract: An active load in an integrated logic circuit of the Direct Coupled FET Logic (DCFL type) in which the active load has a negative threshold voltage and the transistors have a positive threshold voltage. The active load is a transistor, the gate metallization of which is combined with the source metallization. If the active load delivers an excessive current, this current can be adjusted by adding at least one second gate which has a positive threshold voltage and which is in electrical contact with the first gate with a negative threshold voltage. The appropriate threshold voltages are obtained by bombarding the corresponding gate regions. The transistors of the integrated circuit are obtained during the manufacture of the second gate.

Abstract: The invention pertains to programmable fast logic.The logic gate of the invention comprises two parallel-mounted inverters comprising one transistor and one saturable load. The second inverter is powered through a transistor, the electrode gate of which, linked to the drain, is joined to the drain of the first inverter which may have additional inputs (OR function). A triplet of three series-mounted logic gates comprises a programming input at the third gate, a re-looping output and, in the case of a sequence of triplets, re-looping inputs at the first gate of the first triplet. A programmable logic circuit is obtained by a sequence of series-mounted triplets which are all looped back to the first gate of the sequence. The programming is obtained by placing one or two programming inputs at the logic 0 level.Application: Programmable frequency divider circuits in which the ratios follow one another, one by one.

Abstract: A calibrated-weight balance for converting an electrical analog signal to a binary signal as applicable to flash-type analog-to-digital converters is composed of a bistable multivibrator having two transistors (15, 16) and two resistors (25, 26). In the reference channel (15, 25), a current I.sub.0 flows through a resistor (27) connected between drain and ground. In the measuring channel (16, 26), a transistor (17) is connected between a reference voltage (-V.sub.ref) and the drain of the measuring transistor (16). The input of the balance (V.sub.E) is the gate of the third transistor (17). The outputs (Q, Q) of the balance are the drains of the first and second transistors (15, 16). The resistor (26) for supplying the second transistor (16) constitutes the calibrated weight and permits the flow of a current which is a multiple of the current which flows through the resistor (27) of the reference channel.

Abstract: A logic element having low power consumption comprises first lateral PNP transistor whose base and emitter are respectively connected to fixed bias sources, the base voltage being smaller than the emitter voltage, and the collector of said transistor being integral with the base of a transverse NPN transistor integrated into the same substrate, the assembly forming a set of four layers defining three semiconductor junctions. The NPN transistor comprises several emitters, one of which is connected to the base of another NPN transistor whose collector is connected to the output of the device and whose emitter is earthed.