Abstract: An apparatus generally having a first circuit and a plurality of lookup tables is disclosed. The first circuit may be configured to parse a fixed number of bits from a first signal. The bits may contain a variable length code. The lookup tables may be configured to (i) generate a first value, a second value and a third value from a first and a second of the tables based on the bits and (ii) generate a second signal from a third of the tables based on the first value, the second value and the third value. The second signal generally conveys a symbol decoded from the variable length code.