Patents by Inventor Phani Saripella

Phani Saripella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7337418
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Publication number: 20070276871
    Abstract: A model and system employing the model provides an organized structure for storing, displaying, and navigating content data regarding instruments for market driven industries (i.e., securities). A Market Research Model (MRM) paradigm is used to represent elemental concepts, a plurality of specific classes of entities form the MRM, and an interface is used to assemble, maintain, and interact with the model. Information may be added to the model by a research provider and provided to an end user on a subscription basis. The user is provided with an interconnected, navigable model of an item of interest for research and decision-making support.
    Type: Application
    Filed: May 18, 2007
    Publication date: November 29, 2007
    Applicant: PRIMARY GLOBAL RESEARCH, LLC
    Inventors: Michael Fu, Harold Sun, Unni Narayanan, William Ward Carey, Phani Saripella
  • Publication number: 20040010759
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 15, 2004
    Applicant: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Patent number: 6594808
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta