Patents by Inventor Phanindra Bhagavatula

Phanindra Bhagavatula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for measuring the density of a semiconductor device layout
    Patent number: 10671794
    Abstract: A method for determining a density of an integrated circuit layout includes analyzing the IC layout represented by polygons. A portion of the IC layout is analyzed within a sample window located at a sample point. A local density of polygons within the sample window is determined, where an area of one or more of the polygons within the sample window is weighted according to a weighting function giving unequal weight to polygon area based on a position within the sample window. The local density values at each sample point in an array of sample points can be used to determine a layout density and to identify locations of density violations.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 2, 2020
    Assignee: INTEL CORPORATION
    Inventors: Stefan Halama, Saravanan Padmanaban, Phanindra Bhagavatula