Patents by Inventor Phanindra K. Mannava

Phanindra K. Mannava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9392062
    Abstract: Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
  • Patent number: 9148485
    Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 29, 2015
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
  • Publication number: 20150207882
    Abstract: Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.
    Type: Application
    Filed: November 24, 2014
    Publication date: July 23, 2015
    Inventors: MEENAKSHISUNDARAM R. CHINTHAMANI, R. GURU PRASADH, HARI K. NAGPAL, PHANINDRA K. MANNAVA
  • Patent number: 8898393
    Abstract: Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
  • Patent number: 8606934
    Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: December 10, 2013
    Assignee: Intel Corporation
    Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas
  • Publication number: 20130262781
    Abstract: Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.
    Type: Application
    Filed: May 23, 2013
    Publication date: October 3, 2013
    Inventors: MEENAKSHISUNDARAM R. CHINTHAMANI, R. GURU PRASADH, HARI K. NAGPAL, PHANINDRA K. MANNAVA
  • Patent number: 8473567
    Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
  • Patent number: 8468309
    Abstract: Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: June 18, 2013
    Assignee: Intel Corporation
    Inventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
  • Patent number: 8443337
    Abstract: In one embodiment, the present invention includes a method for associating and storing a code fragment for each cell of a table for a protocol specification in a semantic mapping corresponding to the table, and automatically generating a formal model for the protocol specification using the table and the semantic mapping. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: May 14, 2013
    Assignee: Intel Corporation
    Inventors: Ching-Tsun Chou, Phanindra K. Mannava, Seungjoon Park
  • Publication number: 20130103783
    Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.
    Type: Application
    Filed: December 10, 2012
    Publication date: April 25, 2013
    Inventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
  • Publication number: 20120079210
    Abstract: Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.
    Type: Application
    Filed: September 25, 2010
    Publication date: March 29, 2012
    Inventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
  • Publication number: 20110238778
    Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 29, 2011
    Inventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
  • Patent number: 7991875
    Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K. Mannava, Rajee S. Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
  • Patent number: 7953902
    Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 31, 2011
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Victor W. Lee, Aaron T. Spink
  • Patent number: 7937505
    Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: May 3, 2011
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Victor W. Lee, Aaron T. Spink
  • Patent number: 7836144
    Abstract: A system and method for implementing a cache coherency protocol are described. The system includes a first caching agent to send a first cache request to a home agent. The system also includes the home agent including a queue to store the first cache request.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Robert H. Beers, Seungjoon Park, Brannon Batson
  • Patent number: 7831776
    Abstract: A home agent allocates trackers to each of a plurality of caching agents, monitors each caching agent's usage of the allocated trackers, and determines whether a caching agent under-utilizes or over-utilizes them. In the case of under-utilization, the home agent retrieves at least one tracker from the allocation to the caching agent. In the case of over-utilization, the home agent allocates more trackers to the caching agent.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: November 9, 2010
    Assignee: Intel Corporation
    Inventors: Phanindra K Mannava, Vivek Garg, Stan Domen
  • Patent number: 7738484
    Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddaballapur N. Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava
  • Patent number: 7610500
    Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: October 27, 2009
    Assignee: Intel Corporation
    Inventors: Naveen Cherukuri, Jeffrey R. Wilcox, Sanjay Dabral, Phanindra K. Mannava, Aaron T. Spink, David S. Dunning, Tim Frodsham, Theodore Z. Schoenborn
  • Publication number: 20090265472
    Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
    Type: Application
    Filed: January 5, 2009
    Publication date: October 22, 2009
    Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas