Patents by Inventor Phanindra K. Mannava
Phanindra K. Mannava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9392062Abstract: Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.Type: GrantFiled: November 24, 2014Date of Patent: July 12, 2016Assignee: Intel CorporationInventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
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Patent number: 9148485Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.Type: GrantFiled: December 10, 2012Date of Patent: September 29, 2015Assignee: Intel CorporationInventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
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Publication number: 20150207882Abstract: Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.Type: ApplicationFiled: November 24, 2014Publication date: July 23, 2015Inventors: MEENAKSHISUNDARAM R. CHINTHAMANI, R. GURU PRASADH, HARI K. NAGPAL, PHANINDRA K. MANNAVA
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Patent number: 8898393Abstract: Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.Type: GrantFiled: May 23, 2013Date of Patent: November 25, 2014Assignee: Intel CorporationInventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
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Patent number: 8606934Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: GrantFiled: January 5, 2009Date of Patent: December 10, 2013Assignee: Intel CorporationInventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas
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Publication number: 20130262781Abstract: Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.Type: ApplicationFiled: May 23, 2013Publication date: October 3, 2013Inventors: MEENAKSHISUNDARAM R. CHINTHAMANI, R. GURU PRASADH, HARI K. NAGPAL, PHANINDRA K. MANNAVA
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Patent number: 8473567Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.Type: GrantFiled: March 29, 2010Date of Patent: June 25, 2013Assignee: Intel CorporationInventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
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Patent number: 8468309Abstract: Methods and apparatus relating to ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.Type: GrantFiled: September 25, 2010Date of Patent: June 18, 2013Assignee: Intel CorporationInventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
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Patent number: 8443337Abstract: In one embodiment, the present invention includes a method for associating and storing a code fragment for each cell of a table for a protocol specification in a semantic mapping corresponding to the table, and automatically generating a formal model for the protocol specification using the table and the semantic mapping. Other embodiments are described and claimed.Type: GrantFiled: March 11, 2008Date of Patent: May 14, 2013Assignee: Intel CorporationInventors: Ching-Tsun Chou, Phanindra K. Mannava, Seungjoon Park
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Publication number: 20130103783Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.Type: ApplicationFiled: December 10, 2012Publication date: April 25, 2013Inventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
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Publication number: 20120079210Abstract: Methods and apparatus relating to optimized ring protocols and techniques are described. In one embodiment, a first agent generates a request to write to a cache line of a cache over a first ring of a computing platform. A second agent that receives the write request forwards it to a third agent over the first ring of the computing platform. In turn, a third agent (e.g., a home agent) receives data corresponding to the write request over a second, different ring of the computing platform and writes the data to the cache. Other embodiments are also disclosed.Type: ApplicationFiled: September 25, 2010Publication date: March 29, 2012Inventors: Meenakshisundaram R. Chinthamani, R. Guru Prasadh, Hari K. Nagpal, Phanindra K. Mannava
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Publication number: 20110238778Abstract: In one embodiment, the present invention includes a processor that can generate data packets for transmission to an agent, where the processor can generate a data packet having a command portion including a first operation code to encode a transaction type for the data packet and a second operation code to encode a processor-specific operation. This second operation code can encode many different features such as an indication that the data packet is of a smaller size than a standard packet, in order to reduce bandwidth. This operation code can also identify an operation to be performed by a destination agent coupled to the agent. Other embodiments are described and claimed.Type: ApplicationFiled: March 29, 2010Publication date: September 29, 2011Inventors: Phanindra K. Mannava, Hari K. Nagpal, Meenakshisundaram R. Chinthamani, Robert J. Safranek
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Patent number: 7991875Abstract: A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.Type: GrantFiled: January 6, 2006Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Ching-Tsun Chou, Suresh Chittor, Andalib Khan, Akhilesh Kumar, Phanindra K. Mannava, Rajee S. Ram, Sujoy Sen, Srinand Venkatesan, Kiran Padwekar
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Patent number: 7953902Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.Type: GrantFiled: September 30, 2008Date of Patent: May 31, 2011Assignee: Intel CorporationInventors: Phanindra K. Mannava, Victor W. Lee, Aaron T. Spink
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Patent number: 7937505Abstract: A proposal is discussed that facilitates exchanging parameters for a link layer that allows a variable number of parameters without changing a communication protocol. Likewise, the proposal allows for both components connected via the link to negotiate values for the parameters that are exchanged without a need for external agent intervention or redundancy.Type: GrantFiled: September 30, 2008Date of Patent: May 3, 2011Assignee: Intel CorporationInventors: Phanindra K. Mannava, Victor W. Lee, Aaron T. Spink
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Patent number: 7836144Abstract: A system and method for implementing a cache coherency protocol are described. The system includes a first caching agent to send a first cache request to a home agent. The system also includes the home agent including a queue to store the first cache request.Type: GrantFiled: December 29, 2006Date of Patent: November 16, 2010Assignee: Intel CorporationInventors: Phanindra K. Mannava, Robert H. Beers, Seungjoon Park, Brannon Batson
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Patent number: 7831776Abstract: A home agent allocates trackers to each of a plurality of caching agents, monitors each caching agent's usage of the allocated trackers, and determines whether a caching agent under-utilizes or over-utilizes them. In the case of under-utilization, the home agent retrieves at least one tracker from the allocation to the caching agent. In the case of over-utilization, the home agent allocates more trackers to the caching agent.Type: GrantFiled: October 12, 2006Date of Patent: November 9, 2010Assignee: Intel CorporationInventors: Phanindra K Mannava, Vivek Garg, Stan Domen
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Patent number: 7738484Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: GrantFiled: December 13, 2004Date of Patent: June 15, 2010Assignee: Intel CorporationInventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddaballapur N. Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava
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Patent number: 7610500Abstract: Disclosed are embodiments of a method, apparatus and system for a low power state for a point-to-point link. During the low power state, the signal on both conductors of a differential transmit pair are driven to electrical idle. Analog activity detectors are enabled during the low power state and are disabled during normal power state. Exit from the low power state does not require a physical layer re-initialization sequence. Other embodiments are also described and claimed.Type: GrantFiled: December 4, 2007Date of Patent: October 27, 2009Assignee: Intel CorporationInventors: Naveen Cherukuri, Jeffrey R. Wilcox, Sanjay Dabral, Phanindra K. Mannava, Aaron T. Spink, David S. Dunning, Tim Frodsham, Theodore Z. Schoenborn
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Publication number: 20090265472Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.Type: ApplicationFiled: January 5, 2009Publication date: October 22, 2009Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddabaliapur Narasimha-Murthy Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava, Ioannis T. Schoinas