Patents by Inventor Pheak Ti Teh

Pheak Ti Teh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230100829
    Abstract: An integrated circuit package includes a first integrated circuit die, a spacer die coupled in the integrated circuit package in a location designed to house a second integrated circuit die, and a package substrate coupled to the first integrated circuit die and to the spacer die.
    Type: Application
    Filed: November 28, 2022
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Sheue Fen Yong, Archanna Srinivasan, Graham Baker, Pheak Ti Teh
  • Publication number: 20210183758
    Abstract: Disclosed embodiments include conductive polygon power and ground interconnects in an infield formed by an electrical contact array. The conductive polygon ground interconnects are orthogonally reticulated an among the conductive polygon power interconnects, for integrated-circuit device packages that provide a low-loss path to active and passive devices, by minimizing resistive loops.
    Type: Application
    Filed: September 23, 2020
    Publication date: June 17, 2021
    Inventors: Mohd Muhaiyiddin Bin Abdullah, Lee Ping Loh, Pheak Ti Teh, Ken Beng Lim
  • Patent number: 9780040
    Abstract: Techniques for designing integrated circuit (IC) package substrates are provided. One of the provided techniques include routing a first set of interconnects in a first region of an IC package substrate based on a first routing template and routing a second set of interconnects in a second region of the IC package substrate based on a second routing template. The first routing template is associated with output pins on the IC package substrate while the second routing template is associated with interconnects on at least one IC die of the multiple IC dies. In one scenario, the first routing template is a common routing template. As such, when a different IC die is used with an identical, or otherwise similar, IC package substrate, interconnects associated with output pins on that IC package substrate does not need to be rerouted as they may be routed based on the common routing template.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 3, 2017
    Assignee: Altera Corporation
    Inventors: Siow Chek Tan, Swee Fong Chong, Pheak Ti Teh
  • Patent number: 9337240
    Abstract: A lead frame for an integrated circuit (IC) package is disclosed. The lead frame includes a center region and a plurality of lead fingers surrounding the center region. The plurality of lead fingers that surrounds the center region defines a periphery region around the center region. A portion of the plurality of lead fingers extends from the center region to hold the center region in place. Tie bars that are typically used to hold the center region in place may not be included in the lead frame.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 10, 2016
    Assignee: Altera Corporation
    Inventors: Guan Khai Lee, Loon Kwang Tan, Ping Chet Tan, Pheak Ti Teh