Abstract: An isolation resistor is inserted in series between a current source and the emitters of bipolar switching transistors in a differential amplifier. The switching transistors may also be MOSFETs. The in-rush current through the resistor, due to a parasitic or added capacitance, creates a certain increased voltage drop across the resistor, reducing dv/dt and thus reducing the transient in-rush current into the capacitor. This results in reduced waveform distortion. Such an isolation resistor between a current carrying terminal of a switching bipolar transistor and a current source may be used in various applications, including an emitter follower.

Abstract: A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.

Abstract: A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.

Abstract: An isolation resistor is inserted in series between a current source and the emitters of bipolar switching transistors in a differential amplifier. The switching transistors may also be MOSFETs. The in-rush current through the resistor, due to a parasitic or added capacitance, creates a certain increased voltage drop across the resistor, reducing dv/dt and thus reducing the transient in-rush current into the capacitor. This results in reduced waveform distortion. Such an isolation resistor between a current carrying terminal of a switching bipolar transistor and a current source may be used in various applications, including an emitter follower.

Abstract: Current switches are used to control current into the columns during READ operations of a PROM. The circuit provides one such switch for each of the columns of the PROM and makes possible the use of a single current source which is connected to each of the switches but supplies current only to the column of the PROM that is currently selected for reading. A high voltage pre-bias is applied to the collectors of the NPN transistors used as current switches such that turn-on speed is improved because the collector parasitic capacitances are pre-charged to near the supply potential.

Abstract: A redundant memory circuit having a memory for storing information in a matrix of interconnected rows and columns, and a row and a column address decoder to access the rows and columns. The memory has a redundant row or rows to replace a defective row or rows in the matrix and a programmable decoder which is programmed with the row address of the defective row to access the redundant row. The row and column address decoders are used to access the defective row and to sequentially access the columns so as to entirely disconnect the defective row from the columns. The programmable decoder is then programmed with the defective row address, bit by bit, in response to the column addresses, to access the redundant row. After this procedure, a verification circuit can be used to verify that the redundant row can be accessed and that the programmable decoder is properly programmed to decode only one address to one row.