Patents by Inventor Phi Thanh

Phi Thanh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11683890
    Abstract: A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Jonathan W. Thibado, Jeffory L. Smalley, John C. Gulick, Phi Thanh, Mohanraj Prabhugoud
  • Patent number: 11621237
    Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Jonathan W. Thibado, Jeffory L. Smalley, John C. Gulick, Phi Thanh, Mohanraj Prabhugoud, Chong Zhao
  • Patent number: 11545408
    Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a substrate having vias and zones, where the zones have embedded heaters. The heaters may include first traces, second traces, and via filament interconnects. The vias may have a z-height greater than a z-height of the heaters, and each of the zones may have a grid pattern. The RGA interposer may include first and second layers in the substrate, where the first layer includes the first traces, the second layer includes the second traces, and the second layer is over the first layer. The grid pattern may have parallel first traces orthogonal to parallel second traces to form a pattern of squares, where the pattern of squares has the first traces intersect the second traces substantially at right angles.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Jonathan W. Thibado, Jeffory L. Smalley, John C. Gulick, Phi Thanh
  • Patent number: 11488839
    Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 1, 2022
    Assignee: Intel Corporation
    Inventors: Jonathan W. Thibado, Jeffory L. Smalley, John C. Gulick, Phi Thanh
  • Publication number: 20200227362
    Abstract: Embodiments include interposers for use in high speed applications. In an embodiment, the interposer comprises an interposer substrate, and an array of pads on a first surface of the interposer substrate. In an embodiment, a plurality of vias pass through the interposer substrate, where each via is electrically coupled to one of the pads in the array of pads. In an embodiment a plurality of heating elements are embedded in the interposer substrate. In an embodiment a first cable is over the first surface interposer substrate. In an embodiment, the first cable comprises an array of conductive lines along the first cable, where conductive lines proximate to a first end of the cable are electrically coupled to pads in the array of pads.
    Type: Application
    Filed: January 14, 2019
    Publication date: July 16, 2020
    Inventors: Jonathan W. THIBADO, Jeffory L. SMALLEY, John C. GULICK, Phi THANH, Mohanraj PRABHUGOUD, Chong ZHAO
  • Publication number: 20200229294
    Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a substrate having vias and zones, where the zones have embedded heaters. The heaters may include first traces, second traces, and via filament interconnects. The vias may have a z-height greater than a z-height of the heaters, and each of the zones may have a grid pattern. The RGA interposer may include first and second layers in the substrate, where the first layer includes the first traces, the second layer includes the second traces, and the second layer is over the first layer. The grid pattern may have parallel first traces orthogonal to parallel second traces to form a pattern of squares, where the pattern of squares has the first traces intersect the second traces substantially at right angles.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Jonathan W. THIBADO, Jeffory L. SMALLEY, John C. GULICK, Phi THANH
  • Publication number: 20200229309
    Abstract: Embodiments include a reflowable grid array (RGA) interposer, a semiconductor packaged system, and a method of forming the semiconductor packaged system. The RGA interposer includes a plurality of heater traces in a substrate. The RGA interposer also includes a plurality of vias in the substrate. The vias extend vertically from the bottom surface to the top surface of the substrate. The RGA interposer may have one of the vias between two of the heater traces, wherein the vias have a z-height that is greater than a z-height of the heater traces. The heater traces may be embedded in a layer of the substrate, where the layer of the substrate is between top ends and bottom ends of the vias. Each of the plurality of heater traces may include a via filament interconnect coupled to a power source and a ground source. The heater traces may be resistive heaters.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Inventors: Jonathan W. THIBADO, Jeffory L. SMALLEY, John C. GULICK, Phi THANH
  • Publication number: 20200205299
    Abstract: A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Jonathan W. Thibado, Jeffory L. Smalley, John C. Gulick, Phi Thanh, Mohanraj Prabhugoud