Patents by Inventor Phil C. Yeh

Phil C. Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9851946
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: December 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F Cowlishaw, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 9804823
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: October 31, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Sr., Phil C. Yeh
  • Publication number: 20170228195
    Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Inventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, JR., Phil C. Yeh
  • Publication number: 20170199724
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, SR., Phil C. Yeh
  • Patent number: 9690580
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: June 27, 2017
    Assignee: International Business Machines Corporation
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 9690544
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F Cowlishaw, Ronald M. Smith, Sr., Ronald M Smith, Phil C Yeh
  • Patent number: 9652383
    Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, Jr., Phil C. Yeh
  • Publication number: 20170024207
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
    Type: Application
    Filed: October 3, 2016
    Publication date: January 26, 2017
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, SR., Phil C Yeh
  • Publication number: 20160342442
    Abstract: A central processing unit measurement facility is virtualized in order to support concurrent use of the facility by multiple guests executing within a virtual environment. Each guest of the environment has independent control over disablement/enablement of the facility for that guest.
    Type: Application
    Filed: August 4, 2016
    Publication date: November 24, 2016
    Inventors: Lisa Cranton Heller, Patrick M. West, JR., Phil C. Yeh
  • Patent number: 9461668
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: October 4, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 9449314
    Abstract: A central processing unit measurement facility is virtualized in order to support concurrent use of the facility by multiple guests executing within a virtual environment. Each guest of the environment has independent control over disablement/enablement of the facility for that guest.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: September 20, 2016
    Assignee: International Business Machines Corporation
    Inventors: Lisa Cranton Heller, Patrick M. West, Jr., Phil C. Yeh
  • Publication number: 20160202952
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.
    Type: Application
    Filed: March 21, 2016
    Publication date: July 14, 2016
    Inventors: Shawn D. Lundvall, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh
  • Patent number: 9292256
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including a shift significand instruction.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Publication number: 20160070538
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Application
    Filed: November 17, 2015
    Publication date: March 10, 2016
    Inventors: Michael F. Cowlishaw, Eric M. Schwarz, Ronald M. Smith, Phil C. Yeh
  • Publication number: 20160034391
    Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
    Type: Application
    Filed: October 9, 2015
    Publication date: February 4, 2016
    Inventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, JR., Phil C. Yeh
  • Patent number: 9244654
    Abstract: A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Michael F. Cowlishaw, Silvia Melitta Mueller, Eric Schwarz, Phil C. Yeh
  • Patent number: 9201846
    Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: December 1, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael F Cowlishaw, Eric M Schwarz, Ronald M Smith, Sr., Phil C Yeh
  • Patent number: 9158543
    Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: October 13, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, Jr., Phil C. Yeh
  • Publication number: 20140325189
    Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.
    Type: Application
    Filed: July 7, 2014
    Publication date: October 30, 2014
    Inventors: Jane H. Bartik, Lisa C. Heller, Damian L. Osisek, Donald W. Schmidt, Patrick M. West, JR., Phil C. Yeh
  • Publication number: 20140304314
    Abstract: A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format.
    Type: Application
    Filed: June 20, 2014
    Publication date: October 9, 2014
    Inventors: Shawn D Lundvall, Eric M Schwarz, Ronald M Smith, SR., Phil C Yeh