Patents by Inventor Phil Edward Brinkley, Jr.

Phil Edward Brinkley, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Techniques for mitigating, detecting, and correcting single event upset effects
    Patent number: 7620883
    Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: November 17, 2009
    Assignee: XILINX, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.
  • Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
    Patent number: 7512871
    Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: March 31, 2009
    Assignee: XILINX, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.
  • Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
    Patent number: 7383479
    Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: June 3, 2008
    Assignee: Xilinx, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.
  • Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
    Patent number: 7310759
    Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: December 18, 2007
    Assignee: Xilinx, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.
  • Techniques for mitigating, detecting and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
    Patent number: 7036059
    Abstract: SEU mitigation, detection, and correction techniques are disclosed.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: April 25, 2006
    Assignee: Xilinx, Inc.
    Inventors: Carl H. Carmichael, Phil Edward Brinkley, Jr.