Abstract: This invention relates to novel compounds having the structural formula Ia or Ib below: (Ia); (Ib) and to their pharmaceutically acceptable salts, compositions and methods of use. These novel compounds provide a treatment or prophylaxis of cognitive impairment, Alzheimer Disease, neurodegeneration and dementia.

Abstract: This invention relates to novel compounds having the structural formula I below: and to their pharmaceutically acceptable salts, compositions and methods of use. These novel compounds provide a treatment or prophylaxis of cognitive impairment, Alzheimer Disease, neurodegeneration and dementia.

Abstract: This invention relates to novel compounds having the structural formula (I) and to their pharmaceutically acceptable salt, compositions and methods of use. These novel compounds provide a treatment or prophylaxis of cognitive impairment, Alzheimer Disease, neurodegeneration and dementia.

Abstract: This invention relates to novel compounds having the structural formula I below and to their pharmaceutically acceptable salts, compositions and methods of use. These novel compounds provide a treatment or prophylaxis of cognitive impairment, Alzheimer Disease, neurodegeneration and dementia.

Abstract: This invention relates to novel compounds having the structural formula I below: (I) and to their pharmaceutically acceptable salts, compositions and methods of use. These novel compounds provide a treatment or prophylaxis of cognitive impairment, Alzheimer Disease, neurodegeneration and dementia.

Abstract: This invention relates to novel compounds having the structural formula I below: and to their pharmaceutically acceptable salt, compositions and methods of use. These novel compounds provide a treatment or prophylaxis of cognitive impairment, Alzheimer Disease, neurodegeneration and dementia.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic outputs and voter circuits in feedback loops; enhanced triple device redundancy using three FPGAs is introduced to provide nine instances of the user's logic; critical redundant outputs are wire-ANDed together; redundant dual port RAMs, with one port dedicated to refreshing data; and redundant clock delay locked loops (DLL) are monitored and reset if each DLL does not remain in phase with the majority of the DLLs. Detection techniques include: configuration memory readback wherein a checksum is verified; separate FPGAs perform readbacks of configuration memory of a neighbor FPGA; and an FPGA performs a self-readback of its configuration memory array.

Abstract: SEU mitigation, detection, and correction techniques are disclosed.