Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

Abstract: A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.

Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.

Abstract: A system on chip is provided. The system on chip includes a delay control circuit configured to generate delayed clock signals having different delays, based on each of a first rising edge and a first falling edge of an input clock signal, and generate delayed data signals having different delays, based on each of a second rising edge and a second falling edge of an input data signal. The system on chip further includes a de-skew control circuit configured to control the delay control circuit to adjust a delay of each of the first rising edge, the first falling edge, the second rising edge, and the second falling edge.

Abstract: A low voltage differential signaling (LVDS) transmitter may include an LVDS transmission device configured to generate a transmission clock and serial data, which are synchronized to the transmission clock on respective clock and data channels. The transmission clock may have different signal patterns when the LVDS transmission device is operating in normal and de-skew modes of operation. A de-skew controller is also provided, which is electrically coupled to the LVDS transmission device. The de-skew controller is configured to drive the LVDS transmission device with control signals that switch the LVDS transmission device between the normal and de-skew modes of operation. A duty cycle of the transmission clock during the de-skew mode of operation may be unequal to a duty cycle of the transmission clock during the normal mode of operation.

Abstract: A low voltage differential signaling (LVDS) transmitter may include an LVDS transmission device configured to generate a transmission clock and serial data, which are synchronized to the transmission clock on respective clock and data channels. The transmission clock may have different signal patterns when the LVDS transmission device is operating in normal and de-skew modes of operation. A de-skew controller is also provided, which is electrically coupled to the LVDS transmission device. The de-skew controller is configured to drive the LVDS transmission device with control signals that switch the LVDS transmission device between the normal and de-skew modes of operation. A duty cycle of the transmission clock during the de-skew mode of operation may be unequal to a duty cycle of the transmission clock during the normal mode of operation.

Abstract: In a data processing apparatus and a data processing system including the same, the data processing apparatus includes a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; and a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data.

Abstract: A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit. The clock generation unit generates a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit. The mirror delay unit outputs a plurality of delayed preamble signals based on the preamble signal during a preamble period. The preamble phase detection unit provides the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period. The sampling unit extracts data from the data signal by sampling the data signal with the clock signal.

Abstract: In a data processing apparatus and a data processing system including the same, the data processing apparatus includes a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; and a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data.

Abstract: A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.

Abstract: A clock generator based on a phase-locked loop with one pole and an improved period jitter characteristic is disclosed. The clock generator comprises a phase detector for generating a phase detection signal and a phase error signal, a charge pump for generating a loop control voltage, a loop filter for generating an integrated voltage signal, a voltage-controlled oscillator for generating multi-phase output signals, and a phase error compensating circuit for compensating a phase error generated at a prior input clock. The clock generator has an improved period jitter characteristic by compensating a phase error generated at a prior input clock.

Abstract: An apparatus for controlling a delay includes a phase locked loop and a delay unit. The phase locked loop generates an oscillation signal having a frequency substantially identical to that of a reference signal. The delay unit includes a delay cell block that outputs delayed signals by delaying the reference signal sequentially by a uniform delay interval. The delay unit controls the delay interval based on a frequency/phase difference between a first input signal and a second input signal of the phase locked loop, and outputs one of the delayed signals as a delayed reference signal. Related methods are also described.

Abstract: A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit. The clock generation unit generates a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit. The mirror delay unit outputs a plurality of delayed preamble signals based on the preamble signal during a preamble period. The preamble phase detection unit provides the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period. The sampling unit extracts data from the data signal by sampling the data signal with the clock signal.

Abstract: An apparatus for recovering a clock and data includes a transition detecting circuit and a clock recovery circuit. The transition detecting circuit detects a transition of an input data signal to provide a transition interval of the input data signal. The clock recovery circuit generates a recovered clock based on the input data signal during the transition interval of the input data signal.

Abstract: A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.

Abstract: A phase-locked loop circuit including a lock detection function is disclosed. The phase-locked loop circuit comprises a lock detection circuit. The lock detection circuit includes a lock-detection-start-signal generator, a lock-detection-clock generator, and a lock-detection-signal generator. The lock-detection-start-signal generates a lock detection start signal when the pulse width of an up signal and a down signal reaches a predetermined value. The lock-detection-clock generator generates a lock detection clock signal on the basis of the up signal and the down signal. The lock-detection-signal generator counts the lock detection clock signal, and generates the lock detection signal. The phase-locked loop circuit is capable of discriminating the operating regions thereof and outputting a lock detection signal when the locking of phase is completed.

Abstract: A delay-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled delay line and a coarse lock detector. The phase frequency detector generates an up signal and a down signal corresponding to phase and frequency differences between an input clock signal and a feedback signal. The charge pump receives the up signal, the down signal and a coarse lock detection signal to generate a current signal. The loop filter receives and filters the current signal through a low-pass filter to generate a direct voltage signal. The voltage controlled delay line receives the input clock signal and the direct voltage signal to generate the feedback signal and control signals. The coarse lock detector receives the control signals to generate the initialization signal and the coarse lock detection signal to adjust Td within Tin/2<Td<2×Tin when Td?2×Tin or Td?Tin/2.

Abstract: A delay-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled delay line and a coarse lock detector. The phase frequency detector generates an up signal and a down signal corresponding to phase and frequency differences between an input clock signal and a feedback signal. The charge pump receives the up signal, the down signal and a coarse lock detection signal to generate a current signal. The loop filter receives and filters the current signal through a low-pass filter to generate a direct voltage signal. The voltage controlled delay line receives the input clock signal and the direct voltage signal to generate the feedback signal and control signals. The coarse lock detector receives the control signals to generate the initialization signal and the coarse lock detection signal to adjust Td within Tin/2<Td<2×Tin when Td?2×Tin or Td?Tin/2.

Abstract: A phase-locked loop circuit including a lock detection function is disclosed. The phase-locked loop circuit comprises a lock detection circuit. The lock detection circuit includes a lock-detection-start-signal generator, a lock-detection-clock generator, and a lock-detection-signal generator. The lock-detection-start-signal generates a lock detection start signal when the pulse width of an up signal and a down signal reaches a predetermined value. The lock-detection-clock generator generates a lock detection clock signal on the basis of the up signal and the down signal. The lock-detection-signal generator counts the lock detection clock signal, and generates the lock detection signal. The phase-locked loop circuit is capable of discriminating the operating regions thereof and outputting a lock detection signal when the locking of phase is completed.

Abstract: A clock generator based on a phase-locked loop with one pole and an improved period jitter characteristic is disclosed. The clock generator comprises a phase detector for generating a phase detection signal and a phase error signal, a charge pump for generating a loop control voltage, a loop filter for generating an integrated voltage signal, a voltage-controlled oscillator for generating multi-phase output signals, and a phase error compensating circuit for compensating a phase error generated at a prior input clock. The clock generator has an improved period jitter characteristic by compensating a phase error generated at a prior input clock.