Abstract: A memory system with folding error correction. The memory comprises a first memory bank and a second memory bank. A means for generating error correction code for data to be written to said memory system is provided. A means for writing said received data to a location in said first memory bank corresponding to a received address of said received data is provided. Further, a means for generating an error correction code write address in said second memory bank based on said received address. Still further, a means for writing said error correction code to said error correction code write address is provided.

Abstract: The present invention discloses an apparatus and method for performing cyclic redundancy check (CRC) on partial protocol data units (PDUs). The disclosed apparatus is designed to off-load the CRC calculation for transmit or receive from a host computer. According to the disclosed method, when generating CRC for partial PDUs, for each such PDUs a decision is made to determine whether a CRC action is required, i.e., if CRC should be calculated, checked or placed in the outgoing byte stream. When partial CRC calculation is performed the intermediate value is saved into memory and later is used for calculating the CRC for a consecutive partial PDU. In accordance with a preferred embodiment of the invention, the need to re-calculate the CRC in a case of a re-transmit request is eliminated.