Abstract: A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.

Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

Abstract: A method and apparatus for off-chip ESD protection, the apparatus includes an unprotected IC 22 stacked on an ESD protection chip 24 and employing combinations of edge wrap 32 and through-silicon via connectors 44 for electrical connection from an external connection lead 34 on a chip carrier 84 or system substrate 64, to an ESD protection circuit, and to an I/O trace 46 of the unprotected IC 22. In one embodiment the invention provides an ESD-protected stack 50 of unprotected IC chips 52, 54 that has reduced hazard of mechanical and ESD-damage in subsequent handling for assembly and packaging. The method includes a manufacturing method 170 for mass producing embedded edge wrap connectors 32, 38 during the chip manufacturing process.

Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

Abstract: A method and apparatus are described for an electronic component package. A standoff is formed on an active side of a substrate. The substrate has an electronic circuit. A conductive layer is deposited over at least a portion of the active side of the substrate. The conductive layer electrically couples a contact area on the active side of the substrate. The standoff is removed to create a flexible conductor.

Abstract: A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing;is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A method and apparatus for an electronic component package of a passive component using wafer level processing is provided. Posts are formed on the active side of the substrate of an electronic component. A conductive layer leads the contact areas of the electronic component to the tops of the posts. The conductive layer on the top of the posts acting as leads, attaching to traces on a printed circuit board.

Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer.

Abstract: A packaging technique for electronic devices includes wafer fabrication of contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed, via a simple fabrication process, with good wafer packing density. In one embodiment, a trench is formed in the top surface of a substrate parallel to the edge of its electronic circuit. A gold wire extends from a connection point within the circuit into the trench. The gold wire may run over an insulating layer that ends part way through the trench. After epoxy encapsulating the top of the substrate, it is back thinned to expose the bottom surface of the gold wire. Either the back thinning is selective so as to form a substrate standoff, or an epoxy standoff is applied to the bottom of the substrate. A solderable wire runs onto the standoff from the gold wire exposed on the protrusion, possibly over another insulation layer.