Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Abstract: Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.

Abstract: A method of forming an integrated circuit includes providing a buffer layer comprising a dielectric material above a layer of conductive material and providing a layer of mask material above the buffer layer. The mask material comprises amorphous carbon. The method also includes removing a portion of the buffer layer and the layer of mask material to form a mask. A feature is formed in the layer of conductive material according to the mask.

Abstract: Methods are provided for the fabrication of abrupt and tunable offset spacers for improved transistor short channel control. The methods include the formation of a gate electrode within a dielectric layer, with only a top portion of the gate electrode exposed. Silicon is added on the top portion of the gate electrode, by selective epitaxial growth, for example. Etching of the dielectric layer is performed with added silicon at the top portion of the gate electrode serving as a silicon mask to prevent etching of the dielectric layer directly underneath the silicon mask, which includes overhangs over the gate electrode sidewalls. The etching creates offset spacers in a production-worthy manner, and can be used to form offset spacers that are asymmetrical in width. By running the methodology in a microloading regime, wider offset spacers may be created on narrower polysilicon gate features, thereby improving Vt roll-off.

Abstract: The method for forming a semiconductor device arrangement with raised source/drains includes depositing a raised source/drain layer on a substrate, followed by a sacrificial layer on the raised source/drain layer. A trench is formed in the sacrificial layer and the raised source/drain layer, and sidewall spacers are formed within the trench. A replacement gate is formed between the sidewall spacers and the sacrificial layer is removed to expose the raised source/drain regions. The sidewall spacers may then be removed from the sidewalls of the replacement gate, leaving the replacement gate a defined distance from the raised source/drain regions.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: A method and arrangement for reducing the series resistance of the source and drain in a MOSFET device provides for epitaxially grown regions on top of the source and drain extensions to cover portions of the top surfaces of the silicide regions formed on the substrate. The epitaxial material provides an extra flow path for current to flow through to the silicide from the extension, as well as increasing the surface area between the source/drain and the silicide to reduce the contact resistance between the source/drain and the silicide.

Abstract: A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.

Abstract: A method of producing an integrated circuit includes providing a mask definition structure above a layer of conductive material and providing a mask above the layer of conductive material and in contact with at least a portion of the mask definition structure. The mask definition structure comprises a first material and the mask comprises a second material, wherein at least one of the first and second materials comprises amorphous carbon. The mask definition structure is removed, and the layer of conductive material is patterned according to the mask.

Abstract: A method of producing an integrated circuit eliminates the need to re-oxidize polysilicon gate conductors and lines prior to removal of a hard mask used to form the gate conductors. A layer of polysilicon is provided above a semiconductor substrate. The layer of polysilicon is then doped. A mask material comprising amorphous carbon is provided above the layer of polysilicon, and the layer of mask material is patterned to form a mask. A portion of the layer of polysilicon is removed according to the mask, and the mask is removed.

Abstract: A method of forming an integrated circuit using an amorphous carbon hard mask involves providing an amorphous carbon material layer above a layer of conductive material and providing an anti-reflective coating (ARC) material layer above the amorphous carbon material. A transition region is formed intermediate the amorphous carbon material layer and the ARC material layer. The transition region has a concentration profile that provides a transition between the amorphous carbon material layer and the ARC material layer. A portion of the amorphous carbon material layer, the ARC material layer, and the transition region is removed to form a hard mask, and a feature is formed in the layer of conductive material according to the hard mask.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

Abstract: A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

Abstract: A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

Abstract: A semiconductor-on-insulator (SOI) device includes a thermoelectric cooler on a back side of the device. The thermoelectric cooler is formed on a thinned portion of a deep bulk semiconductor layer of the SOI device. The thermoelectric device includes a plurality of pairs of opposite conductivity semiconductor material blocks formed on a metal layer deposited on the thinned portion. The thinning of the thinned portion may be accomplished in multiple etching steps of the deep silicon layer, such as a fast etching down to an etch stop and a slower, more controlled etch to the desired thickness for the thinned portion.

Abstract: A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

Abstract: A hardmask stack is comprised of alternating layers of doped amorphous carbon and undoped amorphous carbon. The undoped amorphous carbon layers serve as buffer layers that constrain the effects of compressive stress within the doped amorphous carbon layers to prevent delamination. The stack is provided with a top capping layer. The layer beneath the capping layer is preferably undoped amorphous carbon to reduce photoresist poisoning. An alternative hardmask stack is comprised of alternating layers of capping material and amorphous carbon. The amorphous carbon layers may be doped or undoped. The capping material layers serve as buffer layers that constrain the effects of compressive stress within the amorphous carbon layers to prevent delamination. The top layer of the stack is formed of a capping material. The layer beneath the top layer is preferably undoped amorphous carbon to reduce photoresist poisoning.

Abstract: A silicon oxide stress relief portion is provided between an amorphous carbon hardmask and a polysilicon layer to be etched to form a gate line. The stress relief portion relieves stress between the hardmask and the polysilicon, thereby reducing the risk of delamination of the hardmask prior to patterning of the polysilicon. The stress relief portion may be trimmed prior to patterning and used as an etch mask for patterning the polysilicon. The amorphous carbon hardmasked may be trimmed prior to patterning the stress relief portion to achieve a further reduction in gate line width.