Abstract: A method of dynamically allocating the amount of input/output (I/O) rate capacity to partitions in a computer system includes determining a total amount of I/O rate capacity and an economic value of each partition within the partitioned computer system. The economic value is defined as a performance-valued product established for each partition wherein the sum of all performance-value products for each partition defines a total economic value for the computer. The I/O rate to be allocated to each partition is calculated to be a portion of the total amount of I/O rate capacity where the portion allocated to each partition is proportional to the economic value of that respective partition. The calculated rate allocations are recorded in memory which is accessible to each partition. After recording, each partition regulates its I/O usage according to the recorded allocation.

Abstract: A computing system having multiple processors in which these processors are configured to support a plurality of workload types may provide processing metering by workload types. In such a system, metering provides a measure of the normalized processing throughput utilized by processing tasks for each workload type supported by the system. This metering measures processing throughput for tasks of any given workload type that is performed by a processor configured to support that workload type as well as tasks of that type which may also be performed on a standard processor.

Abstract: A micro remote data relay receives sensor data from disparate sensors and determines locally whether an alarm condition has occurred. A state machine manages device configuration, memory allocation and usage, algorithm processing of sensor data, and communications. Alarm condition algorithms use data from single sensor or multiple sensors to determine whether an alarm condition has occurred. Sensor data is stored locally. A subset of sensor data and alarm condition reporting is sent to a remote data relay command post allowing monitoring of a perimeter while minimizing data transmission and network usage.

Abstract: A voltage measurement circuit is provided which converts a voltage of a first voltage source connected in series with an offset voltage source to an output voltage, including first and second current mirrors for accurately measuring voltage so as to provide a proportional output voltage with the offset voltage removed. Further, voltage measurements can be precisely determined for each of a plurality of voltage sources, such as a plurality of electrochemical cells in a series electrical connection. By virtue of the voltage measurement circuit, the effect of different offset voltage values on the measured voltage is minimized. Also, the voltage measurement circuit exhibits enhanced stability to variations in operating temperature. Accordingly, accuracy of voltage measurements where offset voltages are present is improved.

Abstract: The battery comprises rechargeable battery cell(s), a current regulator varying a charge current provided to the battery cell(s) and a bypass circuit allowing a discharge current provided by the battery cell(s) to bypass the current regulator. The current regulator can limit the charge current depending on the amperage of the charge current and of the temperature of the current regulator. Two connecting terminals provide the charge current to the battery cell(s) and output the discharge current provided by battery cell(s). This battery can be used in existing applications to replace other type of batteries for which the current-generating equipment of the application for charging the battery was originally designed without requiring modification thereof.

Abstract: A method and system for a partitioned computer system includes the allocation and limiting of input/output (I/O) resources. The method involves reading an I/O key that allocates a system-wide upper limit on I/O resources. The limit may be divided by the number of active partitions within the computer system. Each partition may then be given an equal share of the available I/O resources. If any one partition exceeds the share of resources for that partition, the I/O resource use is capped to meet the maximum limit for that partition. A user may enter the system to customize the initially uniform distribution of I/O resource within the partitioned computer system. Additional partitions may be added or deleted to the computer system. The addition of a partition permits a dynamic reallocation of I/O resource so that a new partition may have a minimal I/O resource allocation for initial operation.

Abstract: A method and system for a partitioned computer system includes the establishment of a computer system where each partition is given an economic value determined by the value of the task to be performed and the processing power assigned to perform the task. The sum of all partitions within the system establishes a fixed economic value for the partitioned system. Billing for utilized processor performance within each partition may be performed in relation to rates established for each partition. Each partition may be assigned a metering key which enables metering and reporting of the processor performance utilization of each partition. Billing reports for each partition may be generated and sent via electronic mail along with a digital signature for each partition to a central billing authority for processing.

Abstract: A system and method for metering usage of a data processing system and scaling system performance is disclosed. In one embodiment, an authorization key is purchased that specifies both a baseline performance level and a ceiling performance level. After the key is installed on the data processing system, the system performance level is monitored and averaged over predetermined time periods. The customer is charged on a “pay-as-you-go” basis for any time periods during which the average performance level exceeds the baseline performance level. Performance of the data processing system is not allowed to exceed the ceiling level obtained with the authorization key. In one embodiment, the baseline level may be set to zero so that all performance consumption is purchased by the customer as it is utilized. A report may be generated that includes data upon which analysis of the measured processor utilization data may be performed.

Abstract: A method and system for a partitioned computer system includes the establishment of a computer system where each partition is given an economic value determined by the value of the task to be performed and the processing power assigned to perform the task. The sum of all partitions within the system establishes a fixed economic value for the partitioned system. Billing for utilized processor performance within each partition may be performed in relation to rates established for each partition. Each partition may be assigned a metering key which enables metering and reporting of the processor performance utilization of each partition. Billing reports for each partition may be generated and sent via electronic mail along with a digital signature for each partition to a central billing authority for processing.

Abstract: A system and method for metering usage of a data processing system and scaling system performance is disclosed. In one embodiment, an authorization key is purchased that specifies both a baseline performance level and a ceiling performance level. The cost of the baseline and ceiling performance levels is included in the price of the key. After the key is installed on the data processing system, the system performance level is monitored and averaged over predetermined time periods. The customer is charged on a “pay-as-you-go” basis for any time periods during which the average performance level exceeds the baseline performance level. Performance of the data processing system is not allowed to exceed the ceiling level obtained with the authorization key. In one embodiment, the baseline level may be set to zero so that all performance consumption is purchased by the customer as it is utilized.

Abstract: A method and system for a partitioned computer system includes the establishment of a computer system where each partition is given an economic value determined by the value of the task to be performed and the processing power assigned to perform the task. The sum of all partitions within the system establishes a fixed economic value for the partitioned system. Billing for utilized processor performance within each partition may be performed in relation to rates established for each partition. Each partition may be assigned a metering key which enables metering and reporting of the processor performance utilization of each partition. Billing reports for each partition may be generated and sent via electronic mail along with a digital signature for each partition to a central billing authority for processing.

Abstract: A current pulse producing, current regulating circuit includes a SCR arranged to pass a current pulse once each positive going half wave input supplied thereto. The SCR is controlled by a control circuit free of current feedback and timing circuitry and responsive to the an unfiltered, rectified A.C. input. The control circuit produces a firing signal, which is applied to the control electrode of the SCR, at a point during the downward swing of each positive going half wave input. The control circuit includes a OR function circuit responsive to the unfiltered rectified input applied to the control circuit and to an output from a circuit also responsive to the unfiltered rectified input; the last mentioned circuit having a hysteresis characteristic. The SCR may be operatively associated with a second SCR and arranged to fire it thereby producing higher amplitude current pulses. Battery charging and forming circuits, as well as off-line power supplies, incorporating the current regulating circuit are disclosed.

Abstract: A battery charger which includes terminals for connection to an electric power source, an electrical charging circuit and an operative arrangement for connecting at least one rechargeable battery cell in series with the charging circuit across the terminals. The battery charger has a charging circuit which includes a first resistor, a second resistor, a third resistor and a rectifier, constituted by at least one diode, in series. A first transistor, which has a collector-emitter path and a base-emitter path, is operatively connected so that the base-emitter path is connected in parallel with the first resistor. A fourth resistor is provided, the fourth resistor being connected in series with the collector-emitter path of the transistor and the third resistor.

Abstract: A power supply which includes terminals for connection to an electric power source, a storage capacitance, an electrical charging circuit and an operative arrangement for connecting storage capacitance in series with the charging circuit across the terminals. The power supply has a charging circuit which includes a first resistor, a second resistor, a third resistor and a rectifier, constituted by at least one diode, in series. A first transistor, which has a collector-emitter path and a base-emitter path, is operatively connected so that the base-emitter path is connected in parallel with the first resistor. A fourth resistor is provided, the fourth resistor being connected in series with the collector-emitter path of the transistor and the third resistor.

Abstract: A power supply which includes terminals for connection to an electric power source, a storage capacitance, an electrical charging circuit and an operative arrangement for connecting the storage capacitance in series with the charging circuit across the terminals. The power supply has a charging circuit which includes a first resistor, a second resistor, a third resistor and a rectifier, constituted by at least one diode, in series. A control stage includes a first transistor, which has a collector-emitter path and a base-emitter path. The transistor is operatively connected so that the base-emitter path is connected in parallel with the first resistor. A fourth resistor is provided, the fourth resistor being connected in series with the collector-emitter path of the transistor and the third resistor.

Abstract: A battery charger which includes terminals for connection to an electric power source, an electrical charging circuit and an operative arrangement for connecting at least one rechargeable battery cell in series with the charging circuit across the terminals. The battery charger has a charging circuit which includes a first resistor, a second resistor, a third resistor and a rectifier, constituted by at least one diode, in series. A first transistor, which has a collector-emitter path and a base-emitter path, is operatively connected so that the base-emitter path is connected in parallel with the first resistor. A fourth resistor is provided, the fourth resistor being connected in series with the collector-emitter path of the transistor and the third resistor.

Abstract: Disclosed is a battery operated hand tool which has incorporated directly into its housing a novel battery charging circuit. The charger normally operates off a conventional household power outlet and comprises a solid state switching circuit for recharging the battery with a series of electrical impulses. In some special cases, it can be operated in a non-switching state. External inductance is eliminated by charging the battery through the hand tool motor.

Abstract: Disclosed is an improved circuit for recharging batteries. It can be used with alternating current power sources having a wide range of voltage and frequencies and also with low voltage direct current power sources. A transistor switch is connected in a feedback circuit to have, in effect, a variable resistance such that the charging current is high when the source potential is low and decreases to zero as the source potential increases. Charging efficiency is thereby significantly increased.