Abstract: A differential logic gate providing complimentary input and complimentary output operation. Transistors (50,52) provide the differential input and emitter follower transistors (54,62) provide the complimentary outputs. Enhanced output high logic levels are enabled by PNP transistors (40,46). PNP transistors (40,46) supply base current drive to transistors (54,62) which boosts the output logic high voltage values presented at terminals (Q,Q-compliment) by reducing collector resistor voltage drop across resistors (42,44). PNP transistors (40,46) remain in their respective conductive states due to voltage regulators (38,48) to provide for faster operation.

Abstract: A receiver circuit (16) is programmable to operate with different logic family driver circuits (10). The receiver circuit has two external configuration pins (22,) 24) that are configured to provide the necessary termination for the type of logic family driver circuit used. To terminate the receiver circuit (16) for an ECL application will require first and second configuration pins (22,24) are connected to VCC—2 volts. To terminate the receiver circuit (16) for a CML application will require the first configuration pin (22) and the second configuration pin (24) are connected to VCC. LVDS termination for the receiver circuit (16) requires the first configuration pin (22) and the second configuration pin (24) are connected together. The configuration pins are external to a semiconductor package (14) housing the receiver circuit.

Abstract: A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.

Abstract: A low power BiMOS output gate includes an input circuit for passing current through its first and second outputs in response to logic states occurring on first and second input signals which are respectively applied at first and second inputs of the input circuit. A field-effect transistor has first and second electrodes and a control electrode, the control electrode is coupled to the first output of the input circuit, the first electrode is coupled to the second output of the input circuit, and the second electrode is coupled to a first supply voltage terminal. A first resistor is coupled across the second and control electrodes of the field-effect transistor while a second resistor is coupled across the first and second electrodes of the field-effect transistor such that when the first input signal is in a first logic state, the voltage drop occurring across the first resistor will render the field-effect transistor operative wherein the effective resistance of the second resistor is decreased.

Abstract: A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.