Abstract: A system and method are disclosed for providing computers, particularly the Unisys A series computers, with the capability to function with disk drives of more than one sector format, especially if a predetermined sector format is inefficient and/or cost prohibitive. Interfacing is provided for processing I/O requests between a predetermined logical sector format (e.g., 180 byte sectors) and a variable physical sector format (e.g., 512 or 720 byte sectors). Read operations compare read request addresses to physical sector boundaries and discard unwanted data. Write operations, using at least one sector buffer, perform a read/modify/write cycle, such that the necessary physical sector data not associated with the write request is read into the sector buffer, modified and written back to the disk along with the write data inserted at the appropriate location. This system and method can effectively increase the usable capacity of selected disk drives by 15-20%.

Abstract: A computer system performs memory to memory transfer, task scheduling and I/O request handling via a group of dedicated processors (e.g. a memory interface unit, an I/O unit, a data transfer unit, and a task control unit). The memory interface unit facilitates data interaction between the memory and the remainder of the system. The I/O unit is coupled to the memory interface unit and performs high level I/O job functions including I/O job scheduling, I/O job path selection, gathering of job statistics and device management. The data transfer unit is coupled to the memory interface unit and moves data between memory locations. The task control unit, coupled to the memory interface unit, allocates and deallocates events, maintains the status of tasks running on the system and schedules the execution of tasks. A hierarchical error reporting scheme is used by all of the processors.

Abstract: The present invention involves the use of multiple I/O processors (204) and (206), configured in parallel in an I/O system (104), to increase system performance as well as enhance system resiliency. Performance is increased by programming one of the multiple I/O processors with the added ability to allocate received I/O job requests among the active I/O processors including itself, thus allowing for parallel processing. The I/O system resiliency is enhanced by ensuring that any one of the I/O processors can assume the tasks of any other I/O processor which may fail. The I/O system described above employs a load balancing algorithm to evenly distribute the I/O job functions among the active I/O processors.

Abstract: An apparatus for preventing bus contention among a plurality of data sources is described which creates signals to be used to disable two of three data sources which share a common bus immediately prior to a bus access cycle. The circuit employs a negative edge triggered flip-flop. This flip-flop generates disable signals which are shifted in phase by 90.degree. with respect to the bus access clock signal. These signals are active one-quarter of a clock cycle before a new bus cycle begins. The early disable serves to clear the bus for access by substantially eliminating the possibility that a slowly responding disabled data source is still active while a quickly responding enabled data source has just become active. The early disabling of the data signals does not result in loss of data. When all data sources on the bus are turned off, a high signal simply goes higher and a low signal rises slowly.

Abstract: A non-return-to-zero synchronizer is described which creates an output pulse signal that is synchronized to a system clock signal, from an asynchronous input strobe signal which can occur at any point in a given system clock cycle. The first circuit element within the synchronizer captures the input strobe and toggles the state of its data output terminal in response to successive pulses of the asynchronous input strobe signal. The remaining portion of the synchronizer responds to each change in the state of the first circuit element and to produce an output pulse having a duration of one clock cycle. An alternative embodiment is described which utilizes a sequential logic circuit to generate the desired output pulse. Because the synchronizer uses a state change to indicate the occurrence of a strobe, the problem of resetting the initial circuit element to a particular logic level is eliminated.