Patents by Inventor Philip A. Saunders

Philip A. Saunders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120064956
    Abstract: A system and method of web-based computer software and hardware is disclosed for recording and analyzing sports statistics to allow a sports team to evaluate the efficiency of its team, players, lineups, games, plays, playbooks, and other related attributes. Computerized algorithms analyze thousands of complex event outcomes based on various user specifications to produce innumerable statistical results. The system is optimized for use on a touch-screen tablet computer but can also be accessed via any computing device with a web browser and an Internet connection. The invention is designed to be used in real-time, but can also be used after the game to record event information or analyze previously recorded data.
    Type: Application
    Filed: September 7, 2011
    Publication date: March 15, 2012
    Applicant: GAMETIME CONCEPTS LLC
    Inventors: Swaptak Das, Panutat Khunachak, Philip Saunders, Ryan Saunders, Stephen Acott
  • Patent number: 7897480
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. Similarly, a method for forming thin to ultra-thin strain Si, SiC, or SiC/Si layers directly on insulator substrates having a strain content in the range of about 1-5% is further described.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Alexander Reznicek, Philip A. Saunders, Leathen Shi
  • Patent number: 7704815
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • Publication number: 20090004831
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Application
    Filed: June 17, 2008
    Publication date: January 1, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • Patent number: 7445977
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • Publication number: 20080261055
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack O. Chu, Alexander Reznicek, Philip A. Saunders, Leathen Shi
  • Publication number: 20070218647
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Application
    Filed: May 4, 2007
    Publication date: September 20, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack Chu, Michael Cobb, Philip Saunders, Leathen Shi
  • Patent number: 7235812
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • Publication number: 20060054891
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Application
    Filed: September 13, 2004
    Publication date: March 16, 2006
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack Chu, Michael Cobb, Philip Saunders, Leathen Shi