Patents by Inventor Philip A. Saunders

Philip A. Saunders has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Preparation of high quality strained-semiconductor directly-on-insulator substrates
    Patent number: 7897480
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. Similarly, a method for forming thin to ultra-thin strain Si, SiC, or SiC/Si layers directly on insulator substrates having a strain content in the range of about 1-5% is further described.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Alexander Reznicek, Philip A. Saunders, Leathen Shi
  • Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
    Patent number: 7704815
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSULATOR (SGOI) SUBSTRATES USING WAFER BONDING TECHNIQUES
    Publication number: 20090004831
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Application
    Filed: June 17, 2008
    Publication date: January 1, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • Method of creating defect free high Ge content (> 25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
    Patent number: 7445977
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: November 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi
  • PREPARATION OF HIGH QUALITY STRAINED-SEMICONDUCTOR DIRECTLY-ON-INSULATOR SUBSTRATES
    Publication number: 20080261055
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack O. Chu, Alexander Reznicek, Philip A. Saunders, Leathen Shi
  • Method of creating defect free high Ge content (>25%) SiGe-on-insulator (SGOI) substrates using wafer bonding techniques
    Patent number: 7235812
    Abstract: A method for achieving a substantially defect free SGOI substrate which includes a SiGe layer that has a high Ge content of greater than about 25 atomic % using a low temperature wafer bonding technique is described. The wafer bonding process described in the present application includes an initial prebonding annealing step that is capable of forming a bonding interface comprising elements of Si, Ge and O, i.e., interfacial SiGeO layer, between a SiGe layer and a low temperature oxide layer. The present invention also provides the SGOI substrate and structure that contains the same.
    Type: Grant
    Filed: September 13, 2004
    Date of Patent: June 26, 2007
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Michael A. Cobb, Philip A. Saunders, Leathen Shi