Abstract: Apparatuses, components, devices, methods, and systems for an adjustable firmness mattress are provided. An example rectangular shaped adjustable firmness mattress extends lengthwise from a head end to a foot end, widthwise from a first side to a second side, and depth-wise from a top side to a bottom side. The example mattress may include an adjustable firmness support layer disposed between the bottom side of the mattress and the top side of the mattress. The adjustable firmness support layer may include at least one rotatable assembly having an orientation-specific firmness, a bridge assembly disposed between the at least one rotatable assembly and the top side of the mattress; and a support assembly disposed between the at least one rotatable assembly and the bottom side of the mattress.

Abstract: A technology is described for a repeater system configured to provide services via a cloud-computing environment. The repeater system can comprise an n-band repeater, wherein n is a positive integer greater than 0; a server port; a donor port; one or more processors and memory in communication with the n-band repeater; and a scanning receiver coupled to the one or more processors and memory, wherein the scanning receiver is configured to scan one or more of the n bands of the n-band repeater and communicate carrier-specific information for the one or more of the n bands to a computer server located in the cloud-computing environment to enable access to the carrier-specific information from the cloud-computing environment.

Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: The use of a sleep, or halt, instruction enables a processor to halt execution when read from a non-volatile memory. The opcode for the sleep instruction is the same value as the constant bit value of an un-programmed, nonvolatile memory. When the opcode is read by the processor, execution is halted and the processor enters a wait or sleep mode. During the sleep mode, firmware is programmed into memory with another means such as an external host processor. When a valid trigger event occurs, for instance, external or internal interrupts or reset activation, the processor then exits the sleep mode and starts instruction etching at the PC_INIT address.

Abstract: An integrated circuit coupled to an external serial bus is presented. A method for prefetching data from an external serial bus is presented. The integrated circuit comprises a serial interface, a data cache, and a prefetch control unit. The serial interface detects a data address on the serial bus and reads data elements from data storage units. The data storage units may be internal or external to the integrated circuit. The data cache is coupled to the serial interface via an internal bus. The prefetch control unit instructs the serial interface to prefetch a data element associated with the data address by reading the data element from a target data storage unit associated with the data address. The data element and the data address are written to the data cache. When a read request is detected, the data element can be quickly accessed from the data cache.

Abstract: A distributed power management system comprising at least two power management integrated circuits PMICs is presented. A master power management integrated circuit PMIC supplies power to a subsystem of an electronic device based on a current state of a master finite state machine FSM executed by the master PMIC. A slave power management integrated circuit PMIC executes a slave finite state machine FSM and supplies power to another subsystem based on the current state of the master FSM. For synchronizing the operation of both PMIC, the master PMIC transmits, to the slave PMIC, synchronization information indicative of at least one of an input signal of the master FSM, a state of the master FSM, a state transition of the master FSM, and an output signal generated by the master FSM. A distributed power management method is presented which is carried out by a master PMIC and a slave PMIC.

Abstract: A debounce circuit eliminates noise, glitches, or transient signal variations resulting from mechanical bounce occurring at a change of state of analog signals and provides a dynamic debounce period alteration and time base variation without loss of the current debounce state. The debounce circuit has a physical counter that is configured for being adjusted within a virtual counter such that the noise, glitches, or transient signal variations resulting from mechanical bounce occurring at an initiation of a change of state of an analog input signal from a source device are filtered by delaying a change of output state of the debounce circuit. The debounce circuit includes a strobe generator that produces a strobe signal that is a submultiple of a master clock that is determined by the location of the physical counter within the virtual counter that is used to increment the physical counter within the virtual counter.

Abstract: A debounce circuit eliminates noise, glitches, or transient signal variations resulting from mechanical bounce occurring at a change of state of analog signals and provides a dynamic debounce period alteration and time base variation without loss of the current debounce state. The debounce circuit has a physical counter that is configured for being adjusted within a virtual counter such that the noise, glitches, or transient signal variations resulting from mechanical bounce occurring at an initiation of a change of state of an analog input signal from a source device are filtered by delaying a change of output state of the debounce circuit. The debounce circuit includes a strobe generator that produces a strobe signal that is a submultiple of a master clock that is determined by the location of the physical counter within the virtual counter that is used to increment the physical counter within the virtual counter.

Abstract: The use of a sleep, or halt, instruction enables a processor to halt execution when read from a non-volatile memory. The opcode for the sleep instruction is the same value as the constant bit value of an un-programmed, nonvolatile memory. When the opcode is read by the processor, execution is halted and the processor enters a wait or sleep mode. During the sleep mode, firmware is programmed into memory with another means such as an external host processor. When a valid trigger event occurs, for instance, external or internal interrupts or reset activation, the processor then exits the sleep mode and starts instruction etching at the PC_INIT address.

Abstract: Patching of program code stored in and directly executed from an OTP is supported by a patch mechanism that does not rely on additional hardware, external intervention or RAM. The features of the disclosure include using a patch daisy chain, delay considerations, non-destructive patching and nested subroutine calls. The techniques disclosed are equally applicable for OTP with an unprogrammed value of “1” as for unprogrammed values of “0”.

Abstract: A novel hand held water-misting apparatus (8) comprising of a latex tubing (10) having a first end and a second end, a valve open-close type (12) having a first end and second end, a misting nozzle (14) having a first end and a second end having a small misting hole, a shrink sleeving (28) securely attaching said valve open-close type (12) and said misting nozzle (14), a water hose connector (16), a flexible strap (26) having a first end and a second end, a pinch clip (24) having an open position and a closed position, an expandable decorative enclosure (18) having a first end and a second end. Said first end of said latex tubing (10) securely attached to said first end of said valve open-close type (12) by a tie clamp (31). Said second end of said latex tubing (10) securely attached to said water hose connector (16) by a tie clamp (30).

Abstract: A novel hand held water-misting apparatus (8) comprising of a latex tubing (10) having a first end and a second end, a valve open-close type (12) having a first end and second end, a misting nozzle (14) having a first end and a second end having a small misting hole, a shrink sleeving (28) securely attaching said valve open-close type (12) and said misting nozzle (14), a water hose connector (16), a flexible strap (26) having a first end and a second end, a pinch clip (24) having an open position and a closed position, an expandable decorative enclosure (18) having a first end and a second end. Said first end of said latex tubing (10) securely attached to said first end of said valve open-close type (12) by a tie clamp (31). Said second end of said latex tubing (10) securely attached to said water hose connector (16) by a tie clamp (30).

Abstract: A piezoelectric circuit (10, 70, 100) is provided, which can be employed in a wide variety of applications. The circuit (10) can be used to test the bulbs in a string (14) of Christmas tree lights and, in a modified circuit (200) can use any suitable high voltage source (202) as a substitute for the piezoelectric crystal. In another circuit (100) a capacitor (72) is used to store electrical power to light a light source (19) for a period of time after the piezoelectric crystal is struck. The circuit (100) can be mounted in a shoe (64), fishing lure (46), toy (56), or any other suitable application to light a light source (19). In another circuit (70) by positioning a capacitor (72) in parallel with the rectified output of crystal (16) and light source (62), and positioning a normally open switch (74) between the capacitor and light source, the capacitor can be charged by repeated striking of the crystal.

Abstract: A piezoelectric circuit (10, 70, 100) is provided which can be employed in a wide variety of applications. The circuit (10) can be used to test the bulbs in a string (14) of Christmas Tree lights and, in a modified circuit (200) can use any suitable high voltage source (202) as a substitute for the piezoelectric crystal. The circuit (100) can also be mounted in a shoe (64), fishing lure (46), toy (56) or any other suitable application to light a light source (19). In another circuit (70) by positioning a capacitor (72) in parallel with the crystal (16) and light source (62), and positioning a normally open switch (74) between the capacitor and light source, the capacitor can be charged by repeated striking of the crystal. The circuit (70) can be used in the pedal (30) of a bicycle to generate a flashing light easily visible at night. The circuit (70) can also be mounted in a camera (90) or emergency light (36) or any other suitable application.

Abstract: As the tractor and baler are driven straight down the windrow, hay is picked up and placed upon a platform conveyor which transfers the same rearwardly toward the baling chamber, during which transfer a deflector diverts the crop stream into an appropriate one of three axial sections of the chamber as determined by sensing and control mechanism associated with the baler. As the hay builds up in one of the sections, the sensors of the mechanism compare the size of that portion of the bale with the bale portion in the next adjacent chamber section, and once the differential between the two bale portions reaches a certain predetermined level, the control mechanism swings the deflector to its next position, directing hay into that next adjacent section to build up that portion of the bale.