Abstract: Techniques for controlling bandwidth in a core are described. An exemplary core includes a memory bandwidth monitor per thread local to the core, each thread's local bandwidth monitor to at least allocate bandwidth for memory requests originating from the thread according to a class of service level stored in a field of quality of service (QOS) model-specific register (MSR), the class of service level pointed to by a class of service field in a platform quality of service MSR; and execution resources to support execution of at least one thread of the core.

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.

Abstract: Techniques for region-aware memory bandwidth allocation control are described. In an embodiment, an apparatus includes a processing core and control circuitry. The processing core is to execute a plurality of threads. The control circuitry is to control use of memory bandwidth per memory region and per thread.

Abstract: Examples described herein relate to at least one multi-core processor and a circuitry can determine and output energy usage of a process regardless of a core of the at least one multi-core processor that executes the process. The circuitry can determine the energy usage of the process based on cache operations and processor microoperations associated with the process. The energy usage of the process can be based on dynamic capacitance (Cdyn) levels and one or more of: temperature of the at least one multi-core processor, input voltage temperature to the at least one multi-core processor, and/or frequency of the at least one multi-core processor.

Abstract: Techniques and mechanisms to facilitate access to a cache based on a dual basis partition scheme. In an embodiment, a first one or more registers of a processor provide information which describes multiple set-wise partitions of a cache. A second one or more registers of the processor provides additional information which describes multiple way-wise partitions of the cache. A virtual cache is defined as that region of the cache which is both in a particular set-wise partition, and in a particular way-wise partition. In another embodiment, a cache agent of the processor performs operations, based on the set-wise partitioning and the way-wise partitioning, to determine a mapping of one address—which is provided in a memory access request, and which indicates a location in one virtual cache—to another address which indicates another location in a different virtual cache.

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement lockstep of processor cores are described. In one embodiment, a hardware processor comprises a first processor core comprising a first control flow signature register and a first execution circuit, a second processor core comprising a second control flow signature register and a second execution circuit, and at least one signature circuit to perform a first state history compression operation on a first instruction that executes on the first execution circuit of the first processor core to produce a first result, store the first result in the first control flow signature register, perform a second state history compression operation on a second instruction that executes on the second execution circuit of the second processor core to produce a second result, and store the second result in the second control flow signature register.

Abstract: Systems, methods, and apparatuses relating to circuitry to implement lockstep of processor cores are described. In one embodiment, a hardware processor comprises a first processor core comprising a first control flow signature register and a first execution circuit, a second processor core comprising a second control flow signature register and a second execution circuit, and at least one signature circuit to perform a first state history compression operation on a first instruction that executes on the first execution circuit of the first processor core to produce a first result, store the first result in the first control flow signature register, perform a second state history compression operation on a second instruction that executes on the second execution circuit of the second processor core to produce a second result, and store the second result in the second control flow signature register.

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Abstract: The invention provides bupropion analogue compounds capable of inhibiting the reuptake of one or more monoamines. The compounds may selectively bind to one or more monoamine transporters, including those for dopamine, norepinephrine, and serotonin. Such compounds may be used to treat conditions that are responsive to inhibition of the reuptake of monoamines, including addiction, depression, and obesity.

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

Abstract: In various implementations, an anchoring system may include one or more anchors. An anchor may include a first coupling member, a second coupling member, and a plate. The anchor may be coupleable to other anchors and/or objects. The anchoring system may be used to secure an object to a location.

Abstract: The invention provides bupropion analogue compounds capable of inhibiting the reuptake of one or more monoamines. The compounds may selectively bind to one or more monoamine transporters, including those for dopamine, norepinephrine, and serotonin. Such compounds may be used to treat conditions that are responsive to inhibition of the reuptake of monoamines, including addiction, depression, and obesity.

Abstract: The invention provides bupropion analog compounds capable of inhibiting the reuptake of one or more monoamines. The compounds may selectively bind to one or more monoamine transporters, including those for dopamine, norepinephrine, and serotonin. Such compounds may be used to treat conditions that are responsive to inhibition of the reuptake of monoamines, including addiction, depression, and obesity.

Abstract: In various implementations, an anchoring system may include one or more anchors. An anchor may include a first coupling member, a second coupling member, and a plate. The anchor may be coupleable to other anchors and/or objects. The anchoring system may be used to secure an object to a location.

Abstract: The invention generally relates to hapten compounds comprising either (+) methamphetamine or (+) amphetamine conjugated to a linker. Generally speaking, hapten compounds of the invention may be used to elicit an immune response to one or more of (+) methamphetamine, (+) amphetamine, or (+) MDMA.

Abstract: Techniques and mechanisms to manage power states for a system-on-chip (SOC). Multiple modules of the SOC include a first module to perform a task including one or more accesses to a memory. In an embodiment, the SOC is transitioned to one of a path-to-memory-available (PMA) power state and a path-to-memory-not-available (PMNA) power state, where the transition is in response to an indication that, of the multiple modules, only the first module is to access the memory during the task. The PMA power state enables data communication between the memory and the first module and prevents data communication between the memory and any other module of the multiple modules. In another embodiment, the PMNA power state prevents data communication between the memory and any of the multiple modules, but allows a low latency transition from the PMNA power state to the PMA power state.

Abstract: Methods and apparatus to improve throughput and efficiency in memory devices are described. In one embodiment, a memory controller may include scheduler logic to issue read or write requests to a memory device in an optimal fashion, e.g., to maximize bandwidth and/or reduce latency. Other embodiments are also disclosed and claimed.