Abstract: A very long instruction word (VLIW) architecture and method provide for functionally expanding a parcel. The instruction register of the VLIW architecture is divided into a plurality of parcels, each of which has corresponding processing logic. The processing logic performs various functions based on the data within the corresponding parcel. A single parcel, however, can only specify a limited number of functions or include a limited amount of data for processing such that the level of optimization for a given VLIW may be impeded. The selector logic and processing logic, however, allow for data from a non-corresponding parcel to be selected and processed. In this manner, the functions and/or amount of data for processing in a single parcel can be expanded by using data from a non-corresponding parcel.

Abstract: A method and apparatus for reordering memory operations in superscalar or very long instruction word (VLIW) processors is described, incorporating a mechanism that allows for arbitrary distance between reading from memory and using data loaded out-of-order, and that allows for moving load operations earlier in the execution stream. This mechanism tolerates ambiguous memory references. The mechanism executes only one additional instruction for disambiguation purposes, thus producing good performance, and integrates memory disambiguation with speculative execution of instructions. The overhead introduced is only one instruction, and the load operation can be arbitrarily moved earlier in the instruction stream. The mechanism can cope with conflicts that occur as a result of an unexpected combination of store/load instructions, can be used in a coherent multiprocessor context, and combines speculative execution with reordering of memory operations in a way which requires simple hardware support.