Patents by Inventor Philip Benedict Giangarra

Philip Benedict Giangarra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10417361
    Abstract: Embodiments of the present disclosure may include receiving, using a processor, an ASCII file including timing and power parameters associated with a portion of the electronic circuit design. Embodiments may further include analyzing the ASCII file and displaying, at a graphical user interface, information from the ASCII file. Embodiments may also include parsing, via the graphical user interface, the information using one or more user-selectable parameters.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 17, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Michael James Floyd, Philip Benedict Giangarra, Abu Nasser Mohammed Abdullah, Zhengang Hong, Joseph Ralph Horn
  • Patent number: 9189578
    Abstract: Embodiments of the present disclosure may include receiving, at one or more computing devices, the electronic circuit design, wherein the electronic circuit design includes at least one Unified Power Format file. Embodiments may further include generating, using the one or more computing devices, a schematic of a power supply network, based upon, at least in part, the at least one Unified Power Format file, the schematic including one or more power supply network components.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: November 17, 2015
    Assignee: Cadence Design Systems, Inc.
    Inventors: Philip Benedict Giangarra, Michael James Floyd, Leonardo Valencia, Debra Jean Wimpey, Yonghao Chen
  • Patent number: 8726224
    Abstract: The present disclosure relates to a computer-implemented method for electronic design visualization. The method may include providing, using at least one computing device, an electronic design and identifying a plurality of power domains associated with the electronic design. The method may further include associating, using the at least one computing device, at least two of the plurality of power domains with a particular group and displaying one or more of the plurality of power domains in a hierarchical manner.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: May 13, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Philip Benedict Giangarra, Debra Jean Wimpey, Michael James Floyd, Abu Nasser Mohammed Abdullah