Patents by Inventor Philip Biggs
Philip Biggs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180012658Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.Type: ApplicationFiled: September 20, 2017Publication date: January 11, 2018Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
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Patent number: 9786370Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.Type: GrantFiled: February 23, 2016Date of Patent: October 10, 2017Assignee: ARM Ltd.Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
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Publication number: 20170243621Abstract: According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.Type: ApplicationFiled: February 23, 2016Publication date: August 24, 2017Inventors: Robert Campbell Aitken, Vikas Chandra, Bal S. Sandhu, George McNeil Lattimore, Shidhartha Das, John Philip Biggs, Parameshwarappa Anand Kumar Savanth, James Edward Myers
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Patent number: 8922247Abstract: A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device.Type: GrantFiled: November 22, 2010Date of Patent: December 30, 2014Assignee: ARM LimitedInventors: James Edward Myers, David Walter Flynn, John Philip Biggs
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Patent number: 8451026Abstract: An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell.Type: GrantFiled: May 13, 2011Date of Patent: May 28, 2013Assignee: ARM LimitedInventors: John Philip Biggs, James Edward Myers, David William Howard, David Walter Flynn, Carsten Tradowsky
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Patent number: 8451039Abstract: Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.Type: GrantFiled: May 13, 2011Date of Patent: May 28, 2013Assignee: ARM LimitedInventors: James Edward Myers, John Philip Biggs, David Walter Flynn, Carsten Tradowsky
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Publication number: 20120286858Abstract: An integrated circuit, a method of generating a layout of such an integrated circuit using standard cells, and a standard cell library providing such standard cells, are disclosed. The method of generating the layout comprises forming a plurality of rows, and populating each row with a plurality of standard cells chosen in dependence on the functional components required by the integrated circuit, each standard cell having its abutment area abutting the abutment area of at least one adjacent standard cell in the row. Within each row, each standard cell in that row is arranged to have a voltage connection area that is aligned with a common routing track, but with each standard cell having its voltage connection area configured so as not to extend across the entire width of the standard cell.Type: ApplicationFiled: May 13, 2011Publication date: November 15, 2012Inventors: John Philip Biggs, James Edward Myers, David William Howard, David Walter Flynn, Carsten Tradowsky
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Publication number: 20120286850Abstract: Apparatus for storing a data value in the form of a master-slave latch supporting zig-zag power gating is described. A NAND gate 52 at the output of the latch forces a predetermined retention signal value at the output from the latch during a retention mode. A scan multiplexer 42 at the input to the latch selects the scan input, which is the predetermined retention signal from another latch, during the retention mode. Within the latch power gated circuitry 32 is subject to zig-zag power gating using virtual power rails VDDZ and VSSZ so as to reduce the leakage current. State storing circuitry 34 is permanently connected to the power supplies VDDG, VSSG such that it is able to maintain whatever signal value is stored therein during the retention mode.Type: ApplicationFiled: May 13, 2011Publication date: November 15, 2012Applicant: ARM LimitedInventors: James Edward Myers, John Philip Biggs, David Walter Flynn, Carsten Tradowsky
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Publication number: 20110181343Abstract: A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device.Type: ApplicationFiled: November 22, 2010Publication date: July 28, 2011Applicant: Arm LimitedInventors: James Edward Myers, David Walter Flynn, John Philip Biggs
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Publication number: 20110102072Abstract: An integrated circuit 2 includes logic circuitry 4 connected to virtual power rails 6, 8. These virtual power rails are connected via power control transistors 10, 16 to a power supply 14. A power controller 20 produces control signals which determines a number of the power control transistors 10, 16 which are in a conductive state and accordingly controls the virtual power rails to have an intermediate voltage level. The intermediate voltage level may be selected to hold the logic circuitry in a retention mode in which state is retained in the logic circuitry 4, but processing operations are not performed. When the functional mode is re-entered, all of the header and footer transistors 10, 16 may be switched to the conductive state.Type: ApplicationFiled: November 4, 2009Publication date: May 5, 2011Applicant: ARM LIMITEDInventors: Sachin Satish Idgunji, David Walter Flynn, John Philip Biggs
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Patent number: 7863778Abstract: A power controlling integrated circuit cell is provided within an integrated circuit power grid to selectively couple an unswitched power supply input to a switched power supply output. The power controlling integrated circuit cell also includes a power control signal input and a power control signal output for supporting the distribution through the integrated circuit of the power control signal. The power controlling integrated circuit cell has a power switching circuit responsive to a power control input signal received at the power control signal input to selectively connect the switched power supply output to the unswitched power supply input, and a power control signal buffer circuit responsive to the switched power supply output to drive a power control output signal from the power control signal output.Type: GrantFiled: July 25, 2005Date of Patent: January 4, 2011Assignee: ARM LimitedInventors: David Walter Flynn, David William Howard, Dhrumil Gandhi, John Philip Biggs
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Publication number: 20090066164Abstract: A power controlling integrated circuit cell is provided within an integrated circuit power grid to selectively couple an unswitched power supply input to a switched power supply output. The power controlling integrated circuit cell also includes a power control signal input and a power control signal output for supporting the distribution through the integrated circuit of the power control signal. The power controlling integrated circuit cell has a power switching circuit responsive to a power control input signal received at the power control signal input to selectively connect the switched power supply output to the unswitched power supply input, and a power control signal buffer circuit responsive to the switched power supply output to drive a power control output signal from the power control signal output.Type: ApplicationFiled: July 25, 2005Publication date: March 12, 2009Inventors: David Walter Flynn, David William Howard, Dhrumil Gandhi, John Philip Biggs
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Publication number: 20070079826Abstract: An apparatus for delivering humidified gases has a connection manifold (8) adapted to connect with inlet (5) and outlet (6) ports of a slide-on water chamber (2) in a single slide on motion. Connection of the gases inlet (5) and gases outlet (6) ports as well as any additional electrical and/or pneumatic connections are all made in the same slide on motion. The water chamber (2) may include inwardly extending elongate extension tubes (30,31) and at least one of the extension tubes may also have an air bleed aperture (33) to aid filling of the chamber (2).Type: ApplicationFiled: September 17, 2003Publication date: April 12, 2007Applicant: Fisher & Paykel Healthcare LimitedInventors: Martin Kramer, Ian Makinson, Philip Biggs, Philip Dickinson
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Publication number: 20060237012Abstract: An apparatus for delivering humidified gases has a connection manifold adapted to connect with inlet and outlet ports of a slide on water chamber in a single slide on motion. Connection of the gases inlet and gases outlet ports as well as any additional electrical and/or pneumatic connections are all made in the same slide on motion. The water chamber may include inwardly extending elongate extension tubes with one of the extension tubes having an air bleed aperture to aid filling of the chamber.Type: ApplicationFiled: July 5, 2006Publication date: October 26, 2006Inventors: Mohammad Thudor, Ian Makinson, Philip Biggs, Philip Dickinson
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Publication number: 20050081869Abstract: The invention relates to a reconstituted smoking material which comprises a non-polyol aerosol generator, tobacco (optional), binder (optional) and inorganic filler. A further polyol aerosol generator may also be contained in the smoking material. There is also provided a smoking article containing such material in a conventional arrangement or with a core axially disposed within an annulus. A further aspect of the invention is the provision of a polyol or non-polyol aerosol generator disposed in the filter element of a smoking article, which may contain the inventive smoking material. The aerosol material on the filter is eluted into the aerosol of the smoke on burning of the smoking article.Type: ApplicationFiled: August 23, 2004Publication date: April 21, 2005Inventors: Philip Biggs, Richard Gilbert, Kevin McAdam, Bhasker Natarajan
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Publication number: 20040199889Abstract: A system of modeling an integrated circuit is described in which a circuit component model 6 is operated upon by a delay calculator 16 using a subset of associated timing and rule data 20. The delay calculator 16 calculates signal transition delays within the circuit component model 6. The output of the delay calculator 16 is searched to identify corresponding signal transitions within the original model 4. Matching transitions are then updated with the calculated delay information augmented with the full set of associated timing and rule data 23 (with constraint data).Type: ApplicationFiled: January 5, 2004Publication date: October 7, 2004Applicant: ARM LIMITEDInventors: Richard William Earnshaw, John Philip Biggs
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Patent number: 5726914Abstract: An apparatus and method for performance analysis, includes storing configuration table data in a configuration table and identifying a computer process in a library in accordance with the stored data. The computer process and the table data are configured and transmitted to a data gathering circuit in order to collect data, which is transmitted to a visual circuit for display.Type: GrantFiled: June 7, 1995Date of Patent: March 10, 1998Assignee: GSE Systems, Inc.Inventors: Joseph Janovski, Pamela Y. Offutt, Bruce E. Manthey, Wayne L. Huff, Philip A. Biggs
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Patent number: D598311Type: GrantFiled: January 31, 2008Date of Patent: August 18, 2009Assignee: Indian Ocean Medical Inc.Inventors: Marc Walter Tanner, Marko Plevnik, Philip Biggs