Patents by Inventor Philip Browning Johnson
Philip Browning Johnson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095205Abstract: A system includes a bus interface and circuitry. The bus interface is configured to communicate with an external device over a peripheral bus. The circuitry is configured to support a plurality of widgets that perform primitive operations used in implementing peripheral-bus devices, to receive a user-defined configuration, which specifies a user-defined peripheral-bus device as a configuration of one or more of the widgets, and to implement the user-defined peripheral-bus device toward the external device over the peripheral bus, in accordance with the user-defined configuration.Type: ApplicationFiled: November 16, 2022Publication date: March 21, 2024Inventors: Daniel Marcovitch, Liran Liss, Aviad Shaul Yehezkel, Rabia Loulou, Oren Duer, Shahaf Shuler, Chenghuan Jia, Philip Browning Johnson, Gal Shalom, Omri Kahalon, Adi Merav Horowitz, Arpit Jain, Eliav Bar-Ilan, Prateek Srivastava
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Publication number: 20230289212Abstract: Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Jerome F. DULUK, JR., Gentaro HIROTA, Ronny KRASHINSKY, Greg PALMER, Jeff TUCKEY, Kaushik NADADHUR, Philip Browning JOHNSON, Praveen JOGINIPALLY
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Publication number: 20230288471Abstract: Processing hardware of a processor is virtualized to provide a façade between a consistent programming interface and specific hardware instances. Hardware processor components can be permanently or temporarily disabled when not needed to support the consistent programming interface and/or to balance hardware processing across a hardware arrangement such as an integrated circuit. Executing software can be migrated from one hardware arrangement to another without need to reset the hardware.Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Jerome F. DULUK, Gentaro HIROTA, Ronny KRASHINSKY, Greg PALMER, Jeff TUCKEY, Kaushik NADADHUR, Philip Browning JOHNSON, Praveen JOGINIPALLY
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Patent number: 10430356Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.Type: GrantFiled: April 28, 2017Date of Patent: October 1, 2019Assignee: NVIDIA CORPORATIONInventors: M. Wasiur Rashid, Jonathon Evans, Gary Ward, Philip Browning Johnson
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Patent number: 10423424Abstract: Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability.Type: GrantFiled: September 28, 2012Date of Patent: September 24, 2019Assignee: NVIDIA CORPORATIONInventors: Lincoln G. Garlick, Philip Browning Johnson, Rafal Zboinski, Jeff Tuckey, Samuel H. Duncan, Peter C. Mills
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Patent number: 10275275Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.Type: GrantFiled: December 3, 2015Date of Patent: April 30, 2019Assignee: NVIDIA CORPORATIONInventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
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Patent number: 10217183Abstract: A system, method, and computer program product are provided for allocating processor resources to process compute workloads and graphics workloads substantially simultaneously. The method includes the steps of allocating a plurality of processing units to process tasks associated with a graphics pipeline, receiving a request to allocate at least one processing unit in the plurality of processing units to process tasks associated with a compute pipeline, and reallocating the at least one processing unit to process tasks associated with the compute pipeline.Type: GrantFiled: December 20, 2013Date of Patent: February 26, 2019Assignee: NVIDIA CORPORATIONInventors: Gregory S. Palmer, Jerome F. Duluk, Jr., Karim Maher Abdalla, Jonathon S. Evans, Adam Clark Weitkemper, Lacky Vasant Shah, Philip Browning Johnson, Gentaro Hirota
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Patent number: 10180916Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.Type: GrantFiled: December 3, 2015Date of Patent: January 15, 2019Assignee: NVIDIA CORPORATIONInventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
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Publication number: 20180314431Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.Type: ApplicationFiled: April 28, 2017Publication date: November 1, 2018Inventors: M. Wasiur Rashid, Jonathon EVANS, Gary Ward, Philip Browning Johnson
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Publication number: 20170161099Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
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Publication number: 20170161100Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
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Patent number: 9639494Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.Type: GrantFiled: November 1, 2013Date of Patent: May 2, 2017Assignee: NVIDIA CorporationInventors: Jesse Max Guss, Philip Browning Johnson, Chris Marriott, Wojciech Jan Truty
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Patent number: 9594599Abstract: A work distribution unit distributes work batches to general processing clusters (GPCs) based on the number of streaming multiprocessors included in each GPC. Advantageously, each GPC receives an amount of work that is proportional to the amount of processing power afforded by the GPC. Embodiments include a method for distributing batches of processing tasks to two or more general processing clusters (GPCs), including the steps of updating a counter value for each of the two or more GPCs based on the number of enabled parallel processing units within each of the two or more GPCs, and distributing a batch of processing tasks to a first GPC of the two or more GPCs based on a counter value associated with the first GPC and based on a load signal received from the first GPC.Type: GrantFiled: October 14, 2009Date of Patent: March 14, 2017Assignee: NVIDIA CorporationInventors: Philip Browning Johnson, Dale L. Kirkland, Karim M. Abdalla
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Patent number: 9442759Abstract: A time slice group (TSG) is a grouping of different streams of work (referred to herein as “channels”) that share the same context information. The set of channels belonging to a TSG are processed in a pre-determined order. However, when a channel stalls while processing, the next channel with independent work can be switched to fully load the parallel processing unit. Importantly, because each channel in the TSG shares the same context information, a context switch operation is not needed when the processing of a particular channel in the TSG stops and the processing of a next channel in the TSG begins. Therefore, multiple independent streams of work are allowed to run concurrently within a single context increasing utilization of parallel processing units.Type: GrantFiled: December 9, 2011Date of Patent: September 13, 2016Assignee: NVIDIA CorporationInventors: Samuel H. Duncan, Lacky V. Shah, Sean J. Treichler, Daniel Elliot Wexler, Jerome F. Duluk, Jr., Philip Browning Johnson, Jonathon Stuart Ramsay Evans
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Publication number: 20150178879Abstract: A system, method, and computer program product are provided for allocating processor resources to process compute workloads and graphics workloads substantially simultaneously. The method includes the steps of allocating a plurality of processing units to process tasks associated with a graphics pipeline, receiving a request to allocate at least one processing unit in the plurality of processing units to process tasks associated with a compute pipeline, and reallocating the at least one processing unit to process tasks associated with the compute pipeline.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: NVIDIA CORPORATIONInventors: Gregory S. Palmer, Jerome F. Duluk, JR., Karim Maher Abdalla, Jonathon S. Evans, Adam Clark Weitkemper, Lacky Vasant Shah, Philip Browning Johnson, Gentaro Hirota
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Publication number: 20150127860Abstract: One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device.Type: ApplicationFiled: November 1, 2013Publication date: May 7, 2015Applicant: NVIDIA CORPORATIONInventors: Jesse Max GUSS, Philip Browning JOHNSON, Chris MARRIOTT, Wojciech Jan TRUTY
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Patent number: 9001134Abstract: Method, apparatuses, and systems are presented for processing a sequence of images for display using a display device involving operating a plurality of graphics devices, including at least one first graphics device that processes certain ones of the sequence of images, including a first image, and at least one second graphics device that processes certain other ones of the sequence of images, including a second image, delaying processing of the second image by the at least one second graphics device, by a specified duration, relative to processing of the first image by the at least one first graphics device, to stagger pixel data output for the first image and pixel data output for the second image, and selectively providing output from the at least one first graphics device and the at least one second graphics device to the display device.Type: GrantFiled: April 3, 2009Date of Patent: April 7, 2015Assignee: NVIDIA CorporationInventors: Franck R. Diard, Wayne Douglas Young, Philip Browning Johnson
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Patent number: 8947444Abstract: A data structure that includes pointers to vertex attributes and primitive descriptions is generated and then processed within a general processing cluster. The general processing cluster includes a vertex attribute fetch unit that fetches from memory vertex attributes corresponding to the vertices defined by the primitive descriptions.Type: GrantFiled: December 9, 2008Date of Patent: February 3, 2015Assignee: NVIDIA CorporationInventors: Ziyad S. Hakura, Emmett M. Kilgariff, Michael C. Shebanow, James C. Bowman, Philip Browning Johnson, Johnny S. Rhoades, Rohit Gupta
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Patent number: 8810592Abstract: One embodiment of the present invention sets forth a technique for providing primitives and vertex attributes to the graphics pipeline. A primitive distribution unit constructs the batches of primitives and writes inline attributes and constants to a vertex attribute buffer (VAB) rather than passing the inline attributes directly to the graphics pipeline. A batch includes indices to attributes, where the attributes for each vertex are stored in a different VAB. The same VAB may be referenced by all of the vertices in a batch or different VABs may be referenced by different vertices in one or more batches. The batches are routed to the different processing engines in the graphics pipeline and each of the processing engines reads the VABs as needed to process the primitives. The number of parallel processing engines may be changed without changing the width or speed of the interconnect used to write the VABs.Type: GrantFiled: September 30, 2010Date of Patent: August 19, 2014Assignee: NVIDIA CorporationInventors: Ziyad S. Hakura, James C. Bowman, Jimmy Earl Chambers, Philip Browning Johnson, Philip Payman Shirvani
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Patent number: 8698816Abstract: Multiple graphics processors in a graphics processing system are interconnected in a unidirectional or bidirectional ring topology, allowing pixels to transferred from any one graphics processor to any other graphics processor. The system can automatically identify one or more “master” graphics processors to which one or more monitors are connected and configures the links of the ring such that one or more other graphics processors can deliver pixels to the master graphics processor, facilitating distributed rendering operations. The system can also automatically detect the connections or lack thereof between the graphics processors.Type: GrantFiled: December 28, 2010Date of Patent: April 15, 2014Assignee: NVIDIA CorporationInventor: Philip Browning Johnson