Abstract: This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.

Abstract: A processor of an aspect includes a plurality of caches at a plurality of different cache levels. The processor also includes a decode unit to decode a fetch instruction. The fetch instruction is to indicate address information for a memory location, and the fetch instruction is to indicate a cache level of the plurality of different cache levels. The processor also includes a cache controller coupled with the decode unit, and coupled with a cache at the indicated cache level. The cache controller, in response to the fetch instruction, is to store data associated with the memory location in the cache, wherein the fetch instruction is architecturally guaranteed to be completed. Other processors, methods, systems, and machine-readable storage mediums storing instructions are disclosed.

Abstract: This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.