Abstract: A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.

Abstract: A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

Abstract: A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

Abstract: A multi-mode architecture is disclosed for a semiconductor circuit, such as a smart card, microcontroller or another single-chip data processing circuit. The disclosed semiconductor circuit supports at least two modes of operation. A memory management unit restricts each application to a predetermined memory range and enforces certain mode-specific restrictions for each memory partition. In a secure kernel mode, all resources and services on the semiconductor circuit, such as special function registers, are accessible. In an application mode, certain special function registers are not accessible (and thus, the resources associated with such special function registers are also not accessible). The operating system is normally executed in a secure kernel mode, where most, if not all resources are accessible. Likewise, a user application is normally executed in a user mode, where certain resources are not accessible.

Abstract: A method and apparatus are disclosed for initializing an unused semiconductor circuit from an external interface of the semiconductor circuit, such as a serial interface, parallel interface or a Universal Serial Bus (USB). A semiconductor circuit includes an unused state detection circuit that detects when the semiconductor circuit has not previously been booted up. When the semiconductor circuit is first booted up, the unused state detection circuit will automatically activate a boot up procedure. The processor on the semiconductor circuit can obtain the appropriate program code for the boot up process from the external interface. The external interface can be connected to a testing station or another external computing device that provides an instruction stream for execution by the processor to initialize the semiconductor circuit load the non-volatile memory with the appropriate application software.

Abstract: A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.

Abstract: A digital circuit run in conjunction with a system clock signal. The digital circuit includes: a digital logic circuitry regulated by a clock signal and powered by a system current; and a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry. The clocking circuitry includes: a power supply monitor circuitry, communicatively coupled to the power supply, providing a first signal indicative of a predetermined level of system current; and a clock regulation circuitry, communicatively coupled to the power supply circuitry, which outputs the clock signal to the digital logic circuitry in response to the first signal. The clock signal comprises (1) the system clock signal when the first signal is in a first state, and (2) a modified clock signal when the first signal is in a second state.

Abstract: A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

Abstract: A digital circuit run in conjunction with a system clock signal, the digital circuit including: a digital logic circuitry regulated by a clock signal and powered by a system current; a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry, the clock regulation circuitry including: a power supply monitor circuitry, communicatively coupled to the power supply, providing a first signal indicative of a predetermined level of system current; a clock regulation circuitry, communicatively coupled to the power supply circuitry, that outputs the clock signal to the digital logic circuitry in response to the first signal. The clock signal comprising the system clock signal when the first signal is in a first state; and the clock signal comprising a modified clock signal when the first signal is in a second state.

Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Abstract: A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Abstract: By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

Abstract: A memory management unit is disclosed for a single-chip data processing circuit, such as a smart card. The memory management unit (i) partitions a homogeneous memory device to achieve heterogeneous memory characteristics for various regions of the memory device, and (ii) restricts access of installed applications executing in the microprocessor core to predetermined memory ranges. The memory management unit provides two operating modes for the processing circuit. In a secure kernel mode, the programmer can access all resources of the device including hardware control. In an application mode, the memory management unit translates the virtual memory address used by the software creator into the physical address allocated to the application by the operating system in a secure kernel mode during installation. The memory management unit implements memory address checking using limit registers and translates virtual addresses to an absolute memory address using offset registers.

Abstract: An emulator is used to debug software operating on a target micro-controller in a target circuit environment. The emulator contains a field programmable gate array that is programmed to contain an emulated target micro-controller and an emulated monitoring circuit which monitors the operations of the micro-controller. The emulated target micro-controller receives signals from the target circuit environment. The signals from the target circuit environment are communicated to the emulated target micro-controller by one or more channels, such as a data channel and a timing channel. The number of channels is limited so that signals from the target environment do not degrade the performance of the emulator. A host computer contains a software debug program which works with the emulated monitoring circuit to monitor the emulated micro-controller.

Abstract: An FeRAM array replaces ROM, PROM, EPROM, and/or EEPROM in a programmable controlling device and thus provides non-volatile memory cells for code stores, data stores, registers (including peripheral registers), state machines and microcode (if included) in the device. The programmable controlling device contains a processor and non-volatile ferroelectric memory cells as well as a ferroelectric memory array. The array has a code store that holds a program to control the processor, a data store that stores temporary data from the processor, and one or more registers that hold data being manipulated by the processor. The code store, data store and registers are memory mapped onto the non-volatile ferroelectric memory array. The state machines and peripheral registers are made of ferroelectric memory cells. The programmable controlling device may also include microcode that cooperates with the processor to change the function of the processor.

Abstract: The present invention is an enhanced peripheral controller communicating between a microcontroller and multiple peripherals that increases the speed with which configuration data sets are loaded. The enhanced peripheral controller includes a programmable logic array (PLA) and an FeRAM array. A reconfigurable peripheral controller is programmed onto the programmable logic array from a configuration data set for one of multiple peripherals. The reconfigurable peripheral controller is reprogrammed each time a new peripheral is connected to the microcontroller. The FeRAM array contains the configuration data set for programming the reconfigurable peripheral controller onto the programmable logic array. The FeRAM will receive a different configuration data set for each different peripheral to be programmed onto the PLA. Because the FeRAM operates at the speed of RAM, it receives the configuration data set for each peripheral on the fly as the microcontroller operates.

Abstract: A smart card having integrated circuitry including a single chip embedded microcontroller for controlling all processes and transactions that take place on the card. The single chip embedded microcontroller comprises a processor, a non-volatile erasable PROM communicating with the processor for reading and writing information to and from the PROM, and an error check and correction circuit cooperating with the PROM to correct errors occurring during the read and write operations after the PROM has performed a greater number of read and write cycles than its endurance. By such arrangement, the accuracy of the read and write operations on the smart card is maintained beyond the endurance of said PROM, enabling PROM-based smart cards having endurance on the order of 100,000 read and write cycles.