Abstract: Disclosed are systems and methods for generating graphical displays of analyte data and/or health information. In some implementations, the graphical displays are generating based on a self-referential dataset that are modifiable based on identified portions of the data. The modified graphical displays can indicate features in the analyte data of a host.

Abstract: Disclosed are systems and methods for generating graphical displays of analyte data and/or health information. In some implementations, the graphical displays are generating based on a self-referential dataset that are modifiable based on identified portions of the data. The modified graphical displays can indicate features in the analyte data of a host.

Abstract: Systems and methods are disclosed that provide smart alerts to users, e.g., alerts to users about diabetic states that are only provided when it makes sense to do so, e.g., when the system can predict or estimate that the user is not already cognitively aware of their current condition, e.g., particularly where the current condition is a diabetic state warranting attention. In this way, the alert or alarm is personalized and made particularly effective for that user. Such systems and methods still alert the user when action is necessary, e.g., a bolus or temporary basal rate change, or provide a response to a missed bolus or a need for correction, but do not alert when action is unnecessary, e.g., if the user is already estimated or predicted to be cognitively aware of the diabetic state warranting attention, or if corrective action was already taken.

Abstract: A segmented retention closure forms a lid that detachably attaches to a container for holding and orienting an item, such as debris, a gardening tool, a baseball, and a string of lights. The closure comprises a panel and a rim. The rim detachably attaches the panel to an opening of the container. The panel substantially covers an opening in the container. The panel has a perimeter region and a central region. Gaps extend from the perimeter region to the central region. The gaps segregates the panel into panel sections, such that each panel section has freedom to bend, laterally flex, and fold in relation to the other sections. An aperture positions concentric to the panel and in communication with the gap. The aperture also has adjustable size and dimension, such that the aperture and the gap can conform to the shape and dimensions of the item for reception.

Abstract: A method of manufacturing a micro-electrical-mechanical system with thermally isolated active elements. Such a system may embody a bolometer, which is well suited for detecting electromagnetic radiation between 90 GHz and 30 THz while operating at room temperature. The method also discloses a generalized process for manufacturing circuitry incorporating active and passive micro-electrical-mechanical systems in a silicon wafer.

Abstract: A method of manufacturing a micro-electrical-mechanical system with thermally isolated active elements. Such a system may embody a bolometer, which is well suited for detecting electromagnetic radiation between 90 GHz and 30 THz while operating at room temperature. The method also discloses a generalized process for manufacturing circuitry incorporating active and passive micro-electrical-mechanical systems in a silicon wafer.

Abstract: In one embodiment, the disclosure relates to a method for forming a semiconductor power device by depositing a first layer of TiW on a gate region and a source region, depositing a second layer of refractory metal over the first layer of TiW at the gate region, depositing a dielectric stack over the second layer of refractory metal and a portion of the first layer of TiW, depositing an etch stop layer over a portion of the dielectric stack, depositing an interconnect layer over the etch stop layer and the dielectric stack and depositing an etch mask over the interconnect layer.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

Abstract: A capacitive type MEMS switch having a conductor arrangement comprised of first and second RF conductors deposited on a substrate. A bridge member having a central enlarged portion is positioned over the conductor arrangement. In one embodiment, the first RF conductor has an end defining an open area in which is positioned a pull down electrode, with the end of the first RF conductor substantially surrounding the pull down electrode. In another embodiment, two opposed RF conductors, each having ends with first and second branches, define an open area in which a pull down electrode is positioned. A dielectric layer is deposited on the conductor arrangement such that when a pull down voltage is applied to the pull down electrode, the switch impedance is significantly reduced so as to allow signal propagation between the RF conductors.

Abstract: A solid state microwave switch having a plurality of adjacent parallel fingers covered with an oxide layer. One end of a finger is an N+ source region while the other end is an N+ drain region, with a current conducting N region between them. The oxide layer is covered with a gate layer to which a gate signal is applied for control of current between the N+ regions through the N region. The gate layer is highly resistive and has a sheet resistance on the order of millions of ohms per square. The length from the source to drain region is around 2 &mgr;m, and the fingers are spaced with a pitch of around 1 &mgr;m.

Abstract: A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder.The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

Abstract: A memory redundancy circuit is described incorporating a sequential row or column counter associated with a plurality of programmable row or column decoders. The sequential row counter includes a sequence circuit for each programmable row decoder. The sequence circuit and programmable row decoder incorporate fixed and variable threshold transistors such as metal nitride oxide semiconductor (MNOS) transistors. The threshold of the variable threshold transistors are switched in response to address signals and control signals to permit redundancy. A disable circuit is also described to permit removal of the redundancy circuits to permit retest of the other circuits.

Abstract: A semiconductor device structure incorporating the edge of silicon island as a surface for diffusing impurities is described to form the drain and source of an MOS transistor and interconnections therebetween to form semiconductor devices such as MOS transistors, variable threshold MNOS transistors, row decoders for use in memories, memory arrays, interconnect crossovers, and high-voltage transistors. A semiconductor process is described for fabricating the above devices utilizing four or five masks.The invention overcomes the problem of high-density integrated circuits by utilizing the edges of silicon islands on an insulating substrate as well as the upper surface of the islands. In addition, contact metallizations are non-critical because of the Schottky barrier diode formed between aluminum and n-type silicon. Both n and p-type semiconductor devices are described.

Abstract: A memory apparatus having a row and column decoder for controlling the read and write function to a transistor memory pair. A single power/chip select pad is utilized to both power the memory and select the memory chip. External control signals are applied directly to critical internal node within the memory apparatus.

Abstract: An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.

Abstract: An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells composed of variable threshold field effect transistors, means for writing and reading information into and out of the array which includes precharged circuitry to provide predetermined voltages on the gate, source and drain electrodes of the transistors in the array before writing or reading and row decode circuitry on both sides of the array to permit closer spacing of the variable threshold transistors in the array.