Abstract: A radio frequency identification (RFID) tag antenna system includes a planar two arm logarithmic spiral antenna with a suitably small form factor. There are two arms are of conductive foils or etched copper plating on a substrate the extend outwardly from a center in a logarithmic fashion. The two arms are identical to each other but rotated in the plane by 180 degrees. The arms also grow proportionally in width as they extend outward, but at any given distance from the center the width of both arms are equal to each other and, preferably, equal to the spaces between the arms. An impedance matching network receives the RF signal received by the dual spiral antenna and feed the RF signal to an electronic circuit that rectifies and multiplies the signal to form a DC signal that charges a capacitor.

Abstract: A radio frequency identification (RFID) tag antenna system includes a planar two arm logarithmic spiral antenna with a suitably small form factor. There are two arms are of conductive foils or etched copper plating on a substrate the extend outwardly from a center in a logarithmic fashion. The two arms are identical to each other but rotated in the plane by 180 degrees. The arms also grow proportionally in width as they extend outward, but at any given distance from the center the width of both arms are equal to each other and, preferably, equal to the spaces between the arms. An impedance matching network receives the RF signal received by the dual spiral antenna and feed the RF signal to an electronic circuit that rectifies and multiplies the signal to form a DC signal that charges a capacitor.

Abstract: The present application and invention provides a selectively enabled bias for the pass NMOS transistor (10) of an RF switch. Two bias supplies are selectively switched to connect to the source of the NMOS transistor (10). The first higher bias supply turns the NMOS transistor (10) off and the second lower bias supply turns the NMOS transistor (10) on. The selective switch performs a single pole double throw function and may include PMOS transistors (14, 16) with inverse logic signals connected respective gates. Diodes may be used between the PMOS and the NMOS gate to reduce the capacitance load at the NMOS gate. The bias circuitry provides for lower capacitance values in the NMOS transistor (10) for reducing insertion loss, and lower parasitic input to output capacitance thereby providing better isolation when the switch is off. Moreover, when the switch is on the source to substrate and the drain to substrate capacitances are decreased thereby providing better high frequency isolation.

Abstract: The present application and invention provides a selectively enabled bias for the pass NMOS transistor of an RF switch. Two bias supplies are selectively switched to connect to the source of the NMOS transistor. The first higher bias supply turns the NMOS off and the second lower bias supply turns the NMOS on. The selective switch performs a single pole double throw function and may include PMOS transistors with inverse logic signals connected respective gates. Diodes may be used between the PMOS and the NMOS gate to reduce the capacitance load at the NMOS gate. The bias circuitry provides for lower capacitance values in the NMOS reducing insertion loss, and lower parasitic input to output capacitance thereby providing better isolation when the switch is off. Moreover, when the switch is on the source to substrate and the drain to substrate capacitances are decreased thereby providing better high frequency isolation.