Patents by Inventor Philip Chambers

Philip Chambers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NUCLEOSIDE FORMULATION
    Publication number: 20250082664
    Abstract: The present specification relates to a nucleoside formulation which comprises a nucleoside or a phosphate thereof; and an amphipathic cell penetrating RALA peptide. In one embodiment, the nucleoside formulation comprises gemcitabine or a phosphate thereof and the peptide WEARLARALARALARHLARALARALRACEA.
    Type: Application
    Filed: December 15, 2022
    Publication date: March 13, 2025
    Applicant: PHION THERAPEUTICS LTD.
    Inventors: Helen MCCARTHY, Lindsey Ann BENNIE, Philip CHAMBERS
  • Address generators for verifying integrated circuit hardware designs for cache memory
    Patent number: 11868692
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: January 9, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Anthony Wood, Philip Chambers
  • Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
    Publication number: 20210224450
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Application
    Filed: April 2, 2021
    Publication date: July 22, 2021
    Inventors: Anthony Wood, Philip Chambers
  • Address generators for verifying integrated circuit hardware designs for cache memory
    Patent number: 10990726
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: April 27, 2021
    Assignee: Imagination Technologies Limited
    Inventors: Anthony Wood, Philip Chambers
  • Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
    Publication number: 20200250364
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Anthony Wood, Philip Chambers
  • Address generators for verifying integrated circuit hardware designs for cache memory
    Patent number: 10671699
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 2, 2020
    Assignee: Imagination Technologies Limited
    Inventors: Anthony Wood, Philip Chambers
  • Address Generators for Verifying Integrated Circuit Hardware Designs for Cache Memory
    Publication number: 20180260506
    Abstract: Address generators for use in verifying an integrated circuit hardware design for an n-way set associative cache. The address generator is configured to generate, from a reverse hashing algorithm matching the hashing algorithm used by the n-way set associative cache, a list of cache set addresses that comprises one or more addresses of the main memory corresponding to each of one or more target sets of the n-way set associative cache. The address generator receives requests for addresses of main memory from a driver to be used to generate stimuli for testing an instantiation of the integrated circuit hardware design for the n-way set associative cache. In response to receiving a request the address generator provides an address from the list of cache set addresses.
    Type: Application
    Filed: March 7, 2018
    Publication date: September 13, 2018
    Inventors: Anthony Wood, Philip Chambers
  • Benzodiazepine derivatives and pharmaceutical compositions containing them
    Patent number: 7582624
    Abstract: Benzodiazepine derivative of formula (I), and pharmaceutically acceptable salts thereof, are found to be active against RSV.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: September 1, 2009
    Assignee: Arrow Therapeutics Limited
    Inventors: Malcolm Carter, Philip Chambers, Verity Dowdell, Elisa Ann Henderson, Richard David Kelsey, Debra Taylor, Stanley Tyms, Lara Wilson
  • Newcastle disease virus gene clones
    Patent number: 5310678
    Abstract: Recombinant DNA encoding a polypeptide precursor of the HN or F glycoprotein of Newcastle Disease Virus has been prepared and sequenced.
    Type: Grant
    Filed: November 17, 1989
    Date of Patent: May 10, 1994
    Assignee: National Research Development Corporation
    Inventors: Richard W. Bingham, Philip Chambers, Peter T. Emmerson, Neil S. Millar