Patents by Inventor Philip Chong
Philip Chong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9836390Abstract: A method is provided to evaluate impact of a change to code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.Type: GrantFiled: May 11, 2015Date of Patent: December 5, 2017Assignee: Synopsys, Inc.Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
-
Publication number: 20150317236Abstract: A method is provided method to evaluate impact of a change in code of a depended upon component of a system stored in a non-transitory computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a storage device and a second component stored in the storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and determine a second property evaluation corresponding to the second component, is the second component being associated with the first property evaluation.Type: ApplicationFiled: May 11, 2015Publication date: November 5, 2015Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
-
Patent number: 9032376Abstract: A method is provided to evaluate impact of a change in code of a depended upon component of a system stored in a computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a computer readable storage device and a second component stored in the computer readable storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and obtain a second property evaluation corresponding to the second component, wherein the second component is associated with the first property evaluation.Type: GrantFiled: September 26, 2013Date of Patent: May 12, 2015Assignee: Synopsys, Inc.Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
-
Publication number: 20140130020Abstract: A method is provided method to evaluate impact of a change in code of a depended upon component of a system stored in a non-transitory computer readable storage device, upon a dependent component of the system, the method comprising: identifying a dependency relationship between a first component stored in a storage device and a second component stored in the storage device; in response to a determination that the second component depends upon the first component, configuring a computer system to obtain a first property evaluation corresponding to the first component; and in response to obtaining the first property evaluation corresponding to the first component, configuring the computer system to associate the first property evaluation with the second component, and determine a second property evaluation corresponding to the second component, is the second component being associated with the first property evaluation.Type: ApplicationFiled: September 26, 2013Publication date: May 8, 2014Applicant: Coverity, Inc.Inventors: Marat Boshernitsan, Andreas Kuehlmann, Scott McPeak, Philip Chong, Tobias Welp
-
Patent number: 8589845Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: GrantFiled: November 23, 2009Date of Patent: November 19, 2013Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Patent number: 8572540Abstract: Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function.Type: GrantFiled: June 6, 2011Date of Patent: October 29, 2013Assignee: Cadence Design Systems, Inc.Inventors: Philip Chong, Christian Szegedy
-
Patent number: 8307316Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: GrantFiled: March 21, 2011Date of Patent: November 6, 2012Assignee: Cadence Design Systems, Inc.Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Publication number: 20110252389Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: ApplicationFiled: March 21, 2011Publication date: October 13, 2011Applicant: Cadence Design Systems, Inc.Inventors: Christoph ALBRECHT, Philip CHONG, Andreas KUEHLMANN, Ellen SENTOVICH, Roberto PASSERONE
-
Publication number: 20110239177Abstract: Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Philip Chong, Christian Szegedy
-
Patent number: 8028263Abstract: Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing a perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, an abstract flow is computed, target locations of various electronic components to be placed are identified, a relative ordering of electronic components is determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using an incremental placement technique while minimizing the perturbation impact or an total quadratic movement of instances.Type: GrantFiled: August 8, 2008Date of Patent: September 27, 2011Assignee: Cadence Design Systems, Inc.Inventors: Philip Chong, Christian Szegedy
-
Patent number: 7966595Abstract: Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function.Type: GrantFiled: August 13, 2007Date of Patent: June 21, 2011Assignee: Cadence Design Systems, Inc.Inventors: Philip Chong, Christian Szegedy
-
Patent number: 7913210Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: GrantFiled: May 2, 2007Date of Patent: March 22, 2011Assignee: Cadence Design Systems, Inc.Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Patent number: 7743354Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: GrantFiled: May 2, 2007Date of Patent: June 22, 2010Assignee: Cadence Design Systems, Inc.Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Patent number: 7739644Abstract: Disclosed are methods, systems, and computer program products for performing grid morphing technique for computing a spreading of objects over an area such that the final locations of the objects are distributed over the area and such that the final locations of the objects are minimally perturbed from their initial starting locations and the density of objects meets certain constraints. The minimization of perturbation, or stability, of the approaches disclosed, is the key feature which is the principal benefit of the techniques disclosed. The methods described herein may be used as part of a tool for placement or floorplanning of logic gates or larger macroblocks for the design of an integrated circuit.Type: GrantFiled: August 13, 2007Date of Patent: June 15, 2010Assignee: Candence Design Systems, Inc.Inventors: Philip Chong, Christian Szegedy
-
Publication number: 20100115477Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: ApplicationFiled: November 23, 2009Publication date: May 6, 2010Applicant: CADENCE DESIGN SYSTEMS, INC.Inventors: Christoph ALBRECHT, Philip CHONG, Andreas KUEHLMANN, Ellen Sentovich, Roberto Passerone
-
Publication number: 20100037196Abstract: Disclosed are a method, system, and computer program product for implementing incremental placement for an electronic design while predicting and minimizing the perturbation impact arising from incremental placement of electronic components. In some embodiments, an initial placement of an electronic design is identified, the abstract flow is computed, the target locations of various electronic components to be placed are identified, the relative ordering of electronic components are determined, and the placement is then legalized. Furthermore, in various embodiments, the method, system, or computer program product starts with an initial placement of an electronic design and derives a legal placement by using the incremental placement technique while minimizing the perturbation impact or the total quadratic movement of instances.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Applicant: Cadence Design Systems, Inc.Inventors: Philip Chong, Christian Szegedy
-
Patent number: 7624364Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: GrantFiled: May 2, 2007Date of Patent: November 24, 2009Assignee: Cadence Design Systems, Inc.Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Publication number: 20080276209Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Inventors: Christoph ALBRECHT, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Publication number: 20080276210Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Inventors: Christoph ALBRECHT, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone
-
Publication number: 20080276208Abstract: A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to ascertain sequential optimization based design flexibility throughout multiple stages of a design flow.Type: ApplicationFiled: May 2, 2007Publication date: November 6, 2008Inventors: Christoph Albrecht, Philip Chong, Andreas Kuehlmann, Ellen Sentovich, Roberto Passerone