Patents by Inventor Philip Clovis

Philip Clovis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR INDIVIDUALLY CONFIGURING DYNAMIC RANDOM ACCESS MEMORIES SHARING A COMMON COMMAND ACCESS BUS
    Publication number: 20170236567
    Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 17, 2017
    Inventors: FARRUKH AQUIL, MICHAEL DROP, VAISHNAV SRINIVAS, PHILIP CLOVIS
  • SYSTEMS AND METHODS FOR INDIVIDUALLY CONFIGURING DYNAMIC RANDOM ACCESS MEMORIES SHARING A COMMON COMMAND ACCESS BUS
    Publication number: 20170236572
    Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received. MRW is either ignored or implemented by the first DRAM.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 17, 2017
    Inventors: FARRUKH AQUIL, MICHAEL DROP, VAISHNAV SRINIVAS, PHILIP CLOVIS
  • Systems and methods for individually configuring dynamic random access memories sharing a common command access bus
    Patent number: 9734890
    Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 15, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Farrukh Aquil, Michael Drop, Vaishnav Srinivas, Philip Clovis
  • Systems and methods for individually configuring dynamic random access memories sharing a common command access bus
    Patent number: 9734878
    Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: August 15, 2017
    Inventors: Farrukh Aquil, Michael Drop, Vaishnav Srinivas, Philip Clovis