Abstract: System and method for adjusting timing error in a mobile device. In the mobile device, a crystal oscillator (XO) is used by a system timer as the timing source. When the mobile device enters into a sleep mode, the system timer is set to time the duration of the sleep mode. During the sleep mode, a thermistor is used to measure and monitor the temperature changes of the XO. After the sleep mode is over, a processor in the mobile device determines the frequency changes of the XO based on the temperature changes of the XO. Based on the frequency changes of the XO, the processor determines the timing error that may have occurred when the system timer was timing the sleep mode and determines the actual duration of the sleep mode by adjusting the duration timed by the system timer based on the timing error.

Abstract: System and method for adjusting timing error in a mobile device. In the mobile device, a crystal oscillator (XO) is used by a system timer as the timing source. When the mobile device enters into a sleep mode, the system timer is set to time the duration of the sleep mode. During the sleep mode, a thermistor is used to measure and monitor the temperature changes of the XO. After the sleep mode is over, a processor in the mobile device determines the frequency changes of the XO based on the temperature changes of the XO. Based on the frequency changes of the XO, the processor determines the timing error that may have occurred when the system timer was timing the sleep mode and determines the actual duration of the sleep mode by adjusting the duration timed by the system timer based on the timing error.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: A satellite navigation receiver receives a combination of radio frequency signals from satellites in satellite navigation systems and process the radio frequency signals to calculate an approximate current location of the satellite navigation receiver. Satellite acquisition plays an important part in identifying the current location of the satellite navigation receiver. Acquisition involves identifying the satellites in the satellite navigation that can be used to provide navigation information. Fast Fourier transform based acquisition involves using FFT and subsequently inverse FFT (IFFT) to correlate a coarse acquisition (C/A) code transmitted by a satellite with a C/A code locally generated on the GPS receiver to identify and acquire a transmitting satellite.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.

Abstract: System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination.