Abstract: In a network device, a power potential rectifier is adapted to conductively couple a network connector to an integrated circuit that rectifies and passes a power signal and data signal received from the network connector. The power potential rectifier regulates a received power and/or data signal to ensure proper signal polarity is applied to the integrated circuit.

Abstract: Embodiments of the present invention provide a power source equipment (PSE) network device operable to provide a network signal that may include both power and data. This PSE network device includes a network connector and an integrated circuit. The network connector physically couples the PSE network device to the network. The integrated circuit further includes a power feed circuit. This power feed circuit is operable to draw and balance a plurality of power signals from an isolated power supply. Then the power feed circuit may combine and pass the received data signals and power signal as a single network signal. A PSE controller electrically couples to the integrated circuit but is not necessarily part of the integrated circuit. The PSE controller is operable to govern the production and distribution of the power portion of the network signal.

Abstract: Embodiments of the present invention provide a power feed circuit operable to supply an Ethernet power signal to a coupled Ethernet network. This power feed circuit includes a number of input nodes, differential transistor pairs, active control circuits, insertion loss control limit circuits and output nodes. The input nodes receive a first power signal such as that provided by an isolated 48 volt power supply. Each transistor of the differential transistor pairs couples to one input node. These differential transistor pairs draw currents which combine to produce a power signal component of the Ethernet power signal. The active control circuits sense the currents drawn by each transistor and are operable to apply a feedback signal to the differential transistor pairs based on the second circuit. Additionally, the insertion loss control limit circuit may sense the power and/or data rate associated with the data signal component of the Ethernet power signal.

Abstract: Embodiments of the present invention provide a power feed circuit operable to supply an Ethernet power signal to a coupled Ethernet network. This power feed circuit includes a number of input nodes, differential transistor pairs, active control circuits and output nodes. The input nodes receive a first power signal such as that provided by an isolated 48 volt power supply. Each transistor of the differential transistor pairs couples to one input node. These differential transistor pairs produce a second power signal which may be supplied to the Ethernet network. The active control circuits sense the second power signal passed by each transistor and are operable to apply a feedback signal to the differential transistor pairs based on the sensed power signal. At least one twisted pair couples to each differential transistor pair's output node and is operable to pass the Ethernet power signal.

Abstract: In one embodiment of the present invention, an apparatus includes a plurality of gain stages each having a gain greater than one, and which are coupled to create a positive feedback at an oscillation frequency. The gain stages may be formed of transconductance gain stages which may be coupled together as a ring oscillator or a latch type circuit. Such circuits may be used as calibration circuits in which small signal parameters of the gain stages are directly calibrated, and are used in turn to directly calibrate small signal parameters of a target circuit.

Abstract: Various embodiments of the present invention include methods and apparatus for receiving a radio frequency (RF) signal spectrum in a receiver; mixing the RF signal spectrum with a first local oscillator (LO) frequency to obtain a first downmixed signal; and converting the first downmixed signal to a first digital signal using an analog-to-digital converter (ADC) having an adjustable clock frequency selected to avoid interference with the first LO frequency. The adjustable clock frequency may be adjusted by a predetermined amount, by phase modulation, or in other manners.