Patents by Inventor PHILIP DAVID REUSSWIG
PHILIP DAVID REUSSWIG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11354190Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.Type: GrantFiled: February 24, 2021Date of Patent: June 7, 2022Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Rohit Sehgal, Sahil Sharma, Nian Niles Yang, Philip David Reusswig
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Publication number: 20220050747Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.Type: ApplicationFiled: February 24, 2021Publication date: February 17, 2022Inventors: Rohit Sehgal, Sahil Sharma, Nian Niles Yang, Philip David Reusswig
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Patent number: 10832784Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.Type: GrantFiled: April 29, 2020Date of Patent: November 10, 2020Assignee: Western Digital Technologies, Inc.Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
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Publication number: 20200258582Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.Type: ApplicationFiled: April 29, 2020Publication date: August 13, 2020Inventors: Sahil SHARMA, Nian YANG, Philip David REUSSWIG
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Patent number: 10679708Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.Type: GrantFiled: September 17, 2018Date of Patent: June 9, 2020Assignee: Western Digital Technologies, Inc.Inventors: Sahil Sharma, Nian Yang, Philip David Reusswig
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Patent number: 10636504Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.Type: GrantFiled: October 31, 2017Date of Patent: April 28, 2020Assignee: SanDisk Technologies LLCInventors: Philip David Reusswig, Nian Niles Yang, Anubhav Khandelwal
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Publication number: 20200090759Abstract: Disclosed are systems and methods for providing pre-program read to counter wordline failures. A method includes performing a read operation on a first portion of a flash memory in response to an erase operation on a second portion of the flash memory, wherein the first portion comprises a plurality of logical wordlines corresponding to a plurality of physical wordlines of the second portion. The method also includes counting, for each of the plurality of logical wordlines, a number of memory cells exceeding a threshold error voltage and marking defective physical wordlines in a bitmap. The method also includes performing a write operation into a third portion of the flash memory that includes at least one physical wordline marked as defective in the error bitmap, wherein a predetermined data pattern is written to a lower page of the at least one physical wordline.Type: ApplicationFiled: September 17, 2018Publication date: March 19, 2020Inventors: Sahil SHARMA, Nian Yang, Philip David Reusswig
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Patent number: 10381097Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.Type: GrantFiled: October 31, 2017Date of Patent: August 13, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Nian Niles Yang, Grishma Shah, Philip David Reusswig, Zhenlei Shen
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Patent number: 10379754Abstract: A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.Type: GrantFiled: January 20, 2018Date of Patent: August 13, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Philip David Reusswig, Nian Niles Yang, Grishma Shah, Deepak Raghu, Preeti Yadav, Prasanna Desai Sudhir Rao, Smita Aggarwal, Dana Lee
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Patent number: 10347315Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.Type: GrantFiled: October 31, 2017Date of Patent: July 9, 2019Assignee: SanDisk Technologies LLCInventors: Philip David Reusswig, Grishma Shah, Nian Niles Yang
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Patent number: 10289341Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.Type: GrantFiled: June 30, 2017Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Patent number: 10290347Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.Type: GrantFiled: June 30, 2017Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Publication number: 20190130982Abstract: Over a period of operation, non-volatile memory can develop a residual resistance that is impractical to remove. For example, in a NAND string of memory cells, trapped charge may build up in a region between the bit lines and drain side select gates, so that even when all the devices of a NAND string are in an “on” state, the NAND string will not conduct. This effect will skew both hard bit data determinations, indicating the data state of a selected memory cell, and soft bit data determinations which may correlate to the reliability of the hard bit data. Techniques are described to factor in such excessive residual resistance when determining the soft bit data.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: SanDisk Technologies LLCInventors: Philip David Reusswig, Nian Niles Yang, Anubhav Khandelwal
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Publication number: 20190130964Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing a group read refresh. An apparatus includes a plurality of memory groups. An apparatus includes an operation circuit that performs an operation on a selected memory group of a plurality of memory groups. An apparatus includes a remediation circuit that performs a countermeasure operation on an unselected memory group of a plurality of memory groups in response to an operation on a selected memory group.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: SanDisk Technologies LLCInventors: Philip David Reusswig, Grishma Shah, Nian Niles Yang
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Publication number: 20190130989Abstract: Apparatuses, systems, methods, and computer program products are disclosed for performing read mode tuning. An apparatus includes an error rate storage circuit that determines error rate information. An apparatus includes a mode selection circuit that determines a read mode of a plurality of read modes for reading a set of memory cells based on error rate information. The plurality of read modes may include a fast read mode and a normal read mode. An apparatus includes a read circuit that performs a read on a set of memory cells based on a read mode.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Applicant: Western Digital Technologies, Inc.Inventors: Nian Niles Yang, Grishma Shah, Philip David Reusswig, Zhenlei Shen
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Patent number: 10218789Abstract: In an illustrative example, a data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an erasure correcting code engine configured to generate first erasure recovery data and temporary erasure recovery data in a volatile memory at least partially based on first data to be written to the non-volatile memory. The first erasure recovery data is configured to enable a first type of data recovery of the first data, and the temporary erasure recovery data is configured to enable a second type of data recovery of the first data. The controller is further configured to store the first erasure recovery data and the temporary erasure recovery data in the volatile memory and, after verifying that the first data is stored in the non-volatile memory, to discard or modify the temporary erasure recovery data.Type: GrantFiled: October 12, 2017Date of Patent: February 26, 2019Assignee: Western Digital Technologies, Inc.Inventors: Nian Niles Yang, Steven T. Sprouse, Philip David Reusswig, Tienchien Kuo, Xinmiao Zhang
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Publication number: 20190004734Abstract: Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Publication number: 20190006003Abstract: Systems and methods are described for compacting operating parameter sets in a data storage device. Data storage device may be configured to maintain multiple operating parameter sets, each of which stores various parameters for interacting with different memory elements within the device. The data storage device may further be limited in the total number of operating parameter sets that can be maintained in the device at any given time. Thus, the data storage device may be required at various times to combine two or more operating parameter sets, to enable creation of a new operating parameter set. Because each operating parameter set can contain a number of parameters, identification of similar sets for combination can be computationally intensive. To identify similar sets in an efficient manner, a device as disclosed herein is enabled to reduce a dimensionality of each set, and locate similar sets under that reduced dimensionality.Type: ApplicationFiled: June 30, 2017Publication date: January 3, 2019Inventors: Roi Kirshenbaum, Karin Inbar, Idan Goldenberg, Nian Niles Yang, Rami Rom, Alexander Bazarsky, Ariel Navon, Philip David Reusswig
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Publication number: 20180374547Abstract: The temperature of the various devices on a printed circuit board (PCB) can change over time as the PCB is used. Additionally, the various devices on the PCB can have different temperatures at the same time. For example, the closer a device is to a heat source, the greater the temperature. Similarly, the further away from the heat source, the lower the temperature. Thus, otherwise identical devices on a PCB can have different temperatures at the same time, and additionally, the temperatures can change over time. By periodically measuring the temperature of the devices, the thermal disparity for the devices can be efficiently and intelligently managed.Type: ApplicationFiled: June 22, 2017Publication date: December 27, 2018Inventors: Nian Niles YANG, Philip David REUSSWIG, Mrinal KOCHAR, Varuna KAMILA
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Patent number: 10026483Abstract: Techniques disclosed herein cope with cross-temperature effects in non-volatile memory systems. One technology disclosed herein includes an apparatus and method that scrubs a block of non-volatile memory cells responsive to a determination that variance in word line program temperatures in the block exceeds a threshold. Such blocks having large variance in programming temperatures for different word lines can potentially have high BERs when reading. This may be due to the difficulty in having one set of read levels that are optimum for all word lines in the block.Type: GrantFiled: June 28, 2017Date of Patent: July 17, 2018Assignee: Western Digital Technologies, Inc.Inventors: Grishma Shah, Philip David Reusswig, Chris Nga Yee Yip, Nian Niles Yang