Abstract: A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The component carriers include at least one electrically insulating layer structure, and at least one electrically conductive layer structure. The at least one electrically insulating layer structure relates to a respective one of the component carriers. Located closest to the sacrificial structure are pure or unprocessed electrically insulating layers without electrically conductive material therein.

Abstract: A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The sacrificial structure includes a central structure and releasing layers on or over both opposing main surfaces of the central structure The central structure includes a dummy core being covered, in particular fully, on or over both main surfaces thereof with a respective one of two spatially separated sections of separate material, in particular separate dielectric material.

Abstract: Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.

Abstract: A fetch unit configured to, in response to detecting a subroutine call and link instruction, calculate and store a predicted target address for the corresponding subroutine return instruction in a prediction stack, and if certain conditions are met, also cause to be stored in the prediction stack a predicted target instruction bundle. The fetch unit is also configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and if certain conditions are met, cause any valid predicted target instruction bundle in the prediction stack to be the next bundle to be decoded.

Abstract: Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.

Abstract: A vacuum cleaner that includes a suction motor and a filter assembly. The filter assembly surrounds at least part of the suction motor and has a frame to which a filter medium is attached. The filter medium is spaced from a wall of the frame such that an arcuate passageway is defined between the filter medium and the frame. A part of the air expelled by the suction motor enters a first end of the passageway and moves around the passageway in a clockwise direction. A further part of the air expelled by the suction motor enters a second end of the passageway and moves around the passageway in a counter-clockwise direction. Air within the passageway then passes through the filter medium.

Abstract: Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.

Abstract: A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The component carriers include at least one electrically insulating layer structure, and at least one electrically conductive layer structure. The at least one electrically insulating layer structure relates to a respective one of the component carriers. Located closest to the sacrificial structure are pure or unprocessed electrically insulating layers without electrically conductive material therein.

Abstract: A semifinished product with a sacrificial structure and two component carriers releasably formed on opposing main surfaces of the sacrificial structure. The sacrificial structure includes a central structure and releasing layers on or over both opposing main surfaces of the central structure The central structure includes a dummy core being covered, in particular fully, on or over both main surfaces thereof with a respective one of two spatially separated sections of separate material, in particular separate dielectric material.

Abstract: Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.

Abstract: A fetch unit configured to, in response to detecting a subroutine call and link instruction, calculate and store a predicted target address for the corresponding subroutine return instruction in a prediction stack, and if certain conditions are met, also cause to be stored in the prediction stack a predicted target instruction bundle. The fetch unit is also configured to, in response to detecting a subroutine return instruction, use the predicted target address in the prediction stack to determine the address of the next instruction bundle to be fetched, and if certain conditions are met, cause any valid predicted target instruction bundle in the prediction stack to be the next bundle to be decoded.

Abstract: Hardware structures for check pointing a main shift register one or more times which include a circular buffer used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point and an extra data position for each restorable point in time; an update history shift register which has a data position for each check point which is used to store information indicating whether the circular buffer was updated in a particular clock cycle; a pointer that identifies a subset of the data positions of the circular buffer as active data positions; and check point generation logic that derives each check point by selecting a subset of the active data positions based on the information stored in the update history shift register.

Abstract: A hardware structure provides a way for check pointing a main shift register one or more times. The hardware structure includes an extended shift register used to store the data elements most recently shifted onto the main shift register which has an extra data position for each check point. An update history shift register has a data position for each check point which is used to store information indicating whether the extended shift register was updated. Check point generation logic derives each check point by selecting a subset of the data elements stored in the extended shift register based on the information stored in the update history shift register.

Abstract: Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.

Abstract: The present invention provides a method and an apparatus for creating visual representations of farms that enables connecting farms securely. In one embodiment, a visual representation of a first farm and a visual representation of a second farm are created. A visual representation of a secure connection is created. The visual representation of the first farm is associated with a first end of the visual representation of the secure connection. The visual representation of the second farm is associated with the second end of the visual representation of the secure connection.

Abstract: The present invention provides a method and an apparatus for automatic creation of secure connections between segmented resource farms in a utility computing environment. According to one embodiment, farms are automatically created using visual representations of the farms as a specification. A shared subnet is created as the basis of a secure connection, visual representations of one or more farms are associated with the shared subnet to form the secure connection between the one or more farms.

Abstract: Atomic testing of a multiplicity of scenarios includes generating a listing of interacting scenarios which are likely to cause a failure, and testing ones of the scenarios not included in the listing according to a binary search strategy to identify a subset of the scenarios as a source of failure among the scenarios. Additionally, the listing can be updated with newly identified interacting scenarios which are likely to cause a failure.