Abstract: A method is described for temperature endpointing of a CMP process. A temperature sensor (110) detects temperature changes when the CMP polishing process transitions between different materials.

Abstract: A dielectric layer (112) having a HDP liner layer (104) under the dielectric gap-fill layer (106) (e.g., HSQ/SOG). The HDP process has a deposition and a sputter-etch component. The sputter-etch component results in an HDP liner (104) with a sloped edges on a portion (105) of the liner over the metal lead. The HDP liner (104) profile results in an effective decrease in the metal surface area which, in turn, limits the amount of dielectric fill (106) deposited over the lead.

Abstract: A method of making a microelectronic circuit and the connection pattern therefor including the steps of providing a substrate (3), preferably silicon and preferably including a layer of nickel (38) under a layer of gold (36) thereon. Regions are formed on the substrate for connection of electrical components to the substrate using a first metallurgy, preferably gold and a pattern of bumps (5, 7) is formed of a second metallurgy different from the first metallurgy, preferably lead/tin solder. An interconnection pattern is formed on the substrate contacting at least one bump and at least one pad. The pattern of solder bumps is formed by providing a coupon (31) and patterning the bumps on the coupon and applied to the substrate while attached to the coupon, then heated to cause flow of the bumps onto the substrate. The coupon is then removed from the bumps with the bumps remaining on the substrate.

Abstract: The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.