Patents by Inventor Philip E. Heil

Philip E. Heil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THIN FILM TRANSISTORS HAVING RECESSED CONTACT METALLIZATION
    Publication number: 20260006831
    Abstract: Thin film transistors are described. An integrated circuit structure includes a gate electrode. A gate dielectric layer is on the gate electrode. A channel material layer is on the gate dielectric layer. A dielectric layer is over the channel material layer. Source or drain contacts are on the channel material layer. Each of the source or drain contacts includes a semiconductor material layer, a conductive liner within the semiconductor material layer, and a conductive fill within the conductive liner. One, two or all three of the semiconductor material layer, the conductive liner, or the conductive fill has an uppermost surface below an uppermost surface of the dielectric layer.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 1, 2026
    Inventors: Moshe DOLEJSI, Vishak VENKATRAMAN, Deepyanti TANEJA, Van H. LE, Travis W. LAJOIE, Suraj MATHEW, Abhishek Anil SHARMA, Christopher J. WIEGAND, Gregory J. GEORGE, Taniya KEKUNAWELA PATHIRANAGE, Juichin ALCANTARA, Shardul WADEKAR, Philip E. HEIL, Yu-Wen HUANG, Nikhil MEHTA, Joel M. STETTLER
  • Capped magnetic memory
    Patent number: 10256395
    Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the sidewalls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Daniel R. Lamborn, Oleg Golonzka, Christopher J. Wiegand, Philip E. Heil, M D Tofizur Rahman, Rebecca J. Castellano, Tarun Bansal
  • CAPPED MAGNETIC MEMORY
    Publication number: 20180182952
    Abstract: An embodiment includes an apparatus comprising: a magnetic tunnel junction (MTJ), between first and second electrodes, comprising a dielectric layer between fixed and free layers; a dielectric film directly contacting sidewalls of the first electrode; and a metallic layer coupled to the side-walls via the dielectric film; wherein (a) a vertical axis intersects the first and second electrodes and the MTJ but not the metallic layer, (b) a first horizontal axis intersects the metallic layer, the dielectric film, and the first electrode; and (c) a second horizontal axis, between the first horizontal axis and the MTJ, intersects the dielectric film and the first electrode but not the capping layer. Other embodiments are described herein.
    Type: Application
    Filed: June 19, 2015
    Publication date: June 28, 2018
    Inventors: Daniel R. Lamborn, Oleg Golonzka, Christopher J. Wiegand, Philip E. Heil, MD Tofizur Rahman, Rebecca J. Castellano, Tarun Bansal